Nor Flash Forum Discussions

I am a lite bit confused how to Address the Flash Memory while using Quad SPI.

For Basis is used the "CE220823 SMIF Memory Write and Read Operaration" example.

To check the correct addressing i manipulate the example like this:

     - increase PACKET_SIZE to 128

     - remove Comparing rxbuffer and txbuffer.

     - Insert below Step 4: 

so after step 4 the MCU print always the first 4096 Bytes of the externe Flash.

So know i can configure different Addresses to check if the will be address.

uint8_t extMemAddress[MAX_ADDRESS_SIZE] = {0x00, 0x00, 0x00, 0x00};

For example to Addresse number Two:

uint8_t extMemAddress[MAX_ADDRESS_SIZE] = {0x00, 0x00, 0x02, 0x00};

all want right with the Output:

SMIF code example has started

SMIF interrupt is initialized

SMIF hardware block is initialized

================================================================================

1. Erasing 262144 bytes of memory.

2. Reading after Erase. Ensure that the data read is 0xFF for each byte.

Received Data (128 bytes):

-------------------------

0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF

0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF

0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF

0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF

3. Writing data to memory.

Written Data (128 bytes):

-------------------------

0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F

0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F

0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F

0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F

4. Reading back same Add for verification.

Received Data (128 bytes):

-------------------------

0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F

0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F

0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F

0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F

5. Reading back Zero Add for verification.

Received Data (4096 bytes):

-------------------------

0xFF 0xFF 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D

0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D

0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D

0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D

0x7E 0x7F 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF

0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF

0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF ........

0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF

But when i try to address the Memory above 0xFF i can not see how to do this.

For example uint8_t extMemAddress[MAX_ADDRESS_SIZE] = {0x00, 0x01, 0xFF, 0x00};

I just get 0xFF in the first 4096 Bytes.

For example uint8_t extMemAddress[MAX_ADDRESS_SIZE] = {0x00, 0x00, 0xFF, 0x01};

I got the same Result then Addressing {0x00, 0x00, 0xFF, 0x00};

So my Question is how to Address the ext Memory in the right way???

Nachricht geändert durch Julian Müller

Good morning. I would know if S25FL128L flash memory implements wear leveling internally.

Thanks.

Tom

Please tell me the steps about Chip Erase after Power-On.

After Power-On, how long should I wait to send the Chip Erase Commands (555 AA, 2AA 80, 555 AA, 2AA 55, 555 10) ?

What is next?

How to read the data after Power- On?

Thanks

各位好

          其它几家芯片一般通过非易失寄存器、易失寄存器，或者是扩展地址，这三种方式进入或者退出4 byte addr、以及配置quad enable/dis。

我司应用模型大部分通过非易失寄存器/易失寄存器，配置芯片的4 byte addr的进入和退出，以及quad enable/disable等。

         我司研发工程师在使用cypress的flash过程中，发现256/512Mb flash的进入和退出4 byte addr模式的命令其它三家的型号有差异，请帮忙确认是否可以做到统一，谢谢。

下面是1.8V

Hi,

S34MS16G2 NAND, chip size : 2GB

Number of spare bytes per page : 128

Number of pages per block : 2048

Number of blocks per logical unit  : 16384

I can only write in 1GB chip size. I can not write other 1GB chip size.  You can find the bellow my configuration address Cycle Mapping

//        0-8191 Block is write CORRECT */  but   8191- 16384 Block is write FAIL */ due to that ı use to chip size just 1GB area.

//        Nand2AleSet((addr.uiColumnAddr >> 0u) & 0xFF);          // CA0 -CA7  1st Cycle; Column addr

//        Nand2AleSet((addr.uiColumnAddr >> 8u) & 0x0F);          // CA8 -CA11 2nd Cycle; Column addr

//        Nand2AleSet(((addr.uiBlockAddr << 6u) & 0xC0) |           // PLA0 and BA0  3rd Cycle; Block  addr

//                        ((addr.uiPageAddr >> 0u) & 0x3F));                  // PA0 -PA5  3rd Cycle; Page   addr

//        Nand2AleSet((addr.uiBlockAddr >> 2u) & 0xFF);             // BA1 -BA8  4th Cycle; Block  addr

//        Nand2AleSet((addr.uiBlockAddr >> 10u) & 0x0F);           // BA9-BA12 5th Cycle; Block  addr

My second question, ı did not understand "A31 for 16Gb (4 Gb x 4 QDP)" Can you explain that details ? In shortly, How can ı access all 2GB NAND size?

S34MS16G2  datasheet: https://www.mouser.com/datasheet/2/100/002-00464_S34MS16G2_16_Gb_4-Bit_ECC_x8_I_O_and_1.8-933055.pdf

Thank you,

Regards,

İbrahim

Hi,

In Datasheet(P50), it is described as follows,
"1 = Device Busy, a Write Registers (WRR), program, erase or other operation is in progress"

Which command specifically refers to "other operation"?

Best Regards,
Kumada

What is the ESD rating for S25FL128SAGNFI003 NOR Flash?

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