Nor Flash Forum Discussions
Hello,
I have almost the same problem as mentioned in the thread https://community.cypress.com/t5/Nor-Flash/SpansionFFS-with-SLLD-FTL-InitAll-fails/m-p/155153. However, the cause of the problem cannot be the same as in this thread as we are not using any level translator. We are using STM32G483VE MCU and S256FL256LAGMFI NOR flash. We can read id and status registers from the device, so the communication is working. However, when trying to use SpansionFFS, it always ends in the same condition as for JaAr_633041 - on line 274 at io_pim_spansion.c in function pim_ioctl_span_init(). Even though the formatting in FTL_Format() does not return any error, return code of the FTL_InitAll() function is 14 (FTL_ERR_NOT_FORMATTED) as if the formatting did not end correctly. The underlying problem is also the same, it is because FTL_FindSuperSysEB() on line 141 in the file ftl_init.c returns 28019. Then, formatCount is set 26 on line 188 and whole function fails as format is set to FTL_DONT_FORMAT.
In Format.h, we have changed the defines to have 4 KB sectors, 64 KB eblocks.
Preprocessor define __SLLD is defined in the IDE.
Write enable, write disable, sector erase, program, read and read status register commands are implemented in the slld layer.
Before calling any of the FFS APIs, slld_RDIDCmd() can be called and correctly returns 0x01 0x60 0x19 as specified in the datasheet.
We are stuck on this problem for days, do you have any idea what the problem can be?
Thanks in advance,
Karel
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I am from Bosch, North America. Currently working on 8” &12 “ cluster for GM which is production now.
We are working on VAVE /RPP project for the above mentioned clusters and looking for some information related to Memory chips used on the board.
In the production models, there are NOR (S29GL128S10DHB023)and NAND (S99ML04G2B043)flashes. We are replacing them with S29GL064S80DHB023 and S34ML04G200BHB003 respectively. We have already made changes on test samples and proceeding with product validation with the changes.
For GM, we need to fill out a document called part substitution matrix where certain parameters are compared between old and new parts.
Could you please provide the following details for both old and new parts.
- Coefficient of thermal expansion
- Leadframe Base Material
- Plating Materials & Thicknesses (inner layer(by%)/outer layer(by%))[e.g., Ni 0.001-0.002µm/(98%Sn-2%Bi) 0.010-0.20µm]
- Wire bond material
- Industry test standard to test the part (ex AECQ100)?
Could you please provide the information for the parts or direct me to the right contact in cypress to get this information.
Show LessHi,
What is the ESD (HBM) rating for below part number
> S29CL016J1JQFM030
Hello all,
I am looking for the timing diagrams for NOR Flash S70GL02GS11FHA010. I looked at the memory link (https://www.cypress.com/part/s70gl02gs11fha010 ) but I couldn't find them.
Is this information available on the website or do I need to contact Cypress directly?
Thank you
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I am looking for 128Mbyte RAD HARD QSPI Flash Memory
Thank you
Hi,
Customers are considering "S25FL064LAB MFI010" as the boot ROM for the MCU.
The SPI clock output by the MCU is set to 24MHz.
Since the High width / Low width specification of the SPI clock of the MCU is "min.40%", the minimum width is (1/24) x 40% = 16.667ns.
On the other hand, the High width / Low width of the input clock on the NOR Flash side is "min.45%", so it is required 18.75ns.
Q1.
If I use an SPI clock with a frequency of 24MHz and a duty of ± 10% for the S25FL064L, does it work properly?
What happens if there is a problem?
Q2.
Is the duty ratio value "min.45%" of the SPI clock of S25FL064L the same specification regardless of the oscillation frequency?
The maximum input frequency of this NOR Flash is 50MHz. The value of the fluctuation range (50% Psck-5%) for this frequency is considered to have the most severe effect on the NOR Flash setup / hold timing specifications.
Therefore, NOR Flash is designed to meet the timing specifications at 50MHz, so I think that the setup / hold margin is about twice as long as the clock at 24MHz.
Do you agree with my way of thinking?
Best Regards,
Naoaki Morimoto
Show LessHi,
Is there an IBIS model for the CYRS16B512? I'd like to simulate some interfaces with the Microsemi RTG4 to see if I need to add anything.
Thanks,
Drew
Show LessOn an existing medical product, we intend to program the S29GL01GS11DHIV10 before reflow soldering.
Can we rely for a long term data retention ?
Are two reflow cycle reducing the floating gate levels and reducing retention time ? (our expectation is 10 years)
Thanks for the help
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