Nor Flash Forum Discussions

Hello:

I am migrating a design from S25FL127S to S25HL512T NOR flash.  Couple of questions / issues:

• Is the data interface any different in the QSPI mode?
• How do I get a complete datasheet with the interface information?  I have applied for the "early access" program and not received any response.
• Is there a separate data interface document?

I am trying to work on this today and I am disappointed that I cannot find any data interface information on the S25HLT devices on the web.

Thanks for your help !!!

Steve D

Hi,

Can you suggest alternate QSPI flash of size 128Mb and temperature grade -40 to 105C or -40 to 125C and supports dual parallel x8 configuration wit zynq 7000. Please provide part that is in stock. Does S25FL128LAGNFB010 support dual parallel x8 configuration with zynq 7000?

Thanks.

Hi,

Will the S70FS01GS device work with Zynq UltraScale for booting?

Hi, there

I am using the device of S29JL032J70TFI010.

The program operation to this Flash ROM is monitored by Data# Polling processing, and the data is read after completion.
However, an event occurred in which valid data could not be read.

It is interpreted that this event can be avoided by reading twice from the corresponding part below in the data sheet.

*002-00857 Rev. *J Page37
  Even if the device has completed the program or erase operation and DQ7 has valid data,
  the data outputs on DQ15–DQ0 may be still invalid. Valid data on DQ15–DQ0 (or DQ7–DQ0 for x8-only device) will appear on  successive read cycles.

This is a question for this sentence.

1. What kind of event do you want to call attention to in this sentence in the data sheet?
2. Can you tell me why this sentence was written?

Best Regards,
Kumada

I am using the memory verilog model in S29VS-R_VERILOG.zip. When I polling Status[7] after issuing "Buffer to Flash" in Secure Silicon Region, the model always feedback SSR array value instead of Status after programing done (current_state back to "SecSi_ENTRY"). I want to know if this is the expected behavior or something wrong there.

Verilog pieces  (Line# 2434~2460)

SecSi_ENTRY:
begin
if (falling_edge_WRITE)

...
if (oe)  // No status read branch here 
begin
    if (SecAddr == SA_SecSi)
    begin
        READMEM(ReturnAddr(Addr,SecAddr),SecAddr,SS_T);
        Dout_zd = OutputD;
    end
    else
    begin
       READMEM(Addr,SecAddr,Mem_T);
       Dout_zd = OutputD;
    end
end
end

Target SNOR series: S25FL064L , S25FL128L

I would like to protect the area of 256KB with a password lock.
Therefore, the capacity will be insufficient only in security area 2 and area 3.

It seems that the pointer area can also be password locked.
When I use the pointer area, can the size of 256KB be password-locked?

hello Everyone,

The footprint for S25HS01GTDPBHM03 component is not available in it's Datasheet. Please Let me know where can i get the footprint of it. Expecting a quick reply.

Thanks in Advance!

Datasheet Rev L,

In table 8 the size of CFI data and the byte address range are not consistent. Range 00020h~000CEh (Here is also a typo in the table) means the size = 206d - 32d + 1d = 175 but the table scribed 174 which is confusing. 

Also, is the ID/CFI ASO support Continuous & Linear Synchronous Read? The datasheet mentions SSR support both async/sync read but doesn't tell if ID/CFI supports it or not. 

Thank you.

Regards,

Keter