Nor Flash Forum Discussions
Hi,
I'm tryinig to download the full datasheet for S25HL512TDPBHI01. I registered with the Semper Early Access program, yet still I get an "Access denied" (You do not have sufficient privileges for this resource or its parent to perform this action).
Is this a temporary situation, or are there other things I need to do to be able to access said document?
Show LessHello!
I'm using the S29GL512T10FHI010 in our application and encountered a strange behaviour of the Flash. Depending on the rising reset signals edge, the Flash reacts different.
- If the Reset Signal edge is B, the RY/BY#-Signal of the S29GL512T10FHI010 stays high. That's what we expect.
- If the Reset Signal edge is A, the RY/BY#-Signal of the S29GL512T10FHI010 goes low for about 11us. Why does EA (embedded algorythm) start?
More Pictures:
Picture 1: Normal Flash Access - The Reset# Signal has a steadily rising edge and the system is running well.
Picture 2: No Flash Access - The Reset# Signal has a saddle point (see below) and the system can't access the Flash because of internal EAs.
And again, from my point of view, the saddle point on the Reset# signal is between the thresholds for the input voltage. If the saddle point on the Reset# signal is the trigger for internal EA, there should be more info in the datasheet.
Therefore, a detailed specification for the reset input signals would be helpful.
Regards
krueger
We will check how to connect IO3_RESET # of S25Fl064L when not in use.
It is used in SIO mode and has no RESET signal.
At that time, when I connected + 3.3V to IO3_RESET# and executed RDD 9Fh, the expected data could not be read and all Low was output.
When IO3_RESET# was set to NC, the expected data was output when RDID 9Fh was executed.
What could be the reason why it doesn't work with + 3.3V connected to IO3_RESET#?
Also, does it work without problems when a pull-up resistor is connected?
Best Regards,
Kumada
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I need the datasheet with registries description for the S25HL512 flash memory. How can I get it?
Thank you very much for your help.
I am considering replacing S29PL127J60TFI130 with S29PL127J60TFI080.
When comparing the VOH notation of these parts
S29PL127J60TFI130
VOH(min)=2.4V
(IOH=-2mA,VCC=VCCmin,VIO=2.7-3.6V)
S29PL127J60TFI080
VOH(min)=VCC-0.2V
(IOH=-100uA,VIO=VCCmin)
VOH(min)=VCC-0.2V (IOH=-100uA,VIO=VCCmin) and the condition of IOH is different.
Is the VOH of S29PL127J60TFI080 the same level of performance as that of S29PL127J60TFI130?
Also, if you know the maximum possible output value of IOH, please let me know.
Show LessHi,
Can I get thermal resistance theta j-a, theta j-b, theta j-c, and max junction temperature of S70FL01GSAGBHIC10 device?
Short one..
To read device id and manufacturer id from dual die S70GL02GT device, what would be the command sequence ?
We are using device in x16 mode.
a) Is it this ..
< 2 Byte writes at addresses.>
*(u16 *) 555 = 0xaaaa // unlock 1
*(u16 *) 2AA = 0x5555 // unlock 2
*(u16 *) 555 = 0x9090 // Command.
Read flash device at base address for first die
and set A26 high for second die and repeat a) ?
Hello,
We are using a S25FL128SAGNFI001 128Mbit flash memory and I notice that in our old design I am reviewing that we directly connect the nWP and the nHOLD pins to Vcc=+3V3.
I understand from the datasheet that these pins are internally pulled high to Vcc.
My question is, would connecting them externally without any pull up to +3V3 cause any problem?
Thank you
Show LessDatasheet Rev L, In Chapter 7.2.4 it was written :
"The 8th word will continue to be driven until the burst operation is aborted (CE# goes to VIH, a new address is latched in for a new burst operation, or a hardware reset)."
But in Figure 13. it shows that the A/DQ pins turn into unknow after RDY disable.
The two are not consistent so make me confused, could you help update it?
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