Nor Flash

Hello,

We are a small EMS located in Stockholm, Sweden. One of our customers have chosen the Nor Flash circuit S29GL256S11DHIV20 (an FBGA-64 case) for one of their latest projects.

The customer has tasked us with finding out if this circuit can be programmed by us before we mount it on their boards. We have limited experience with pre-programming chips in BGA-casings, though, and are not sure how to proceed with their request.

Is there an suitable hardware adapter for fitting a BGA-capsule (without damaging the balls) adn does there exist a software package for flashing the circuit this way?

Hello.

My customer requested the pad information of S25FS512SDSMFB010.
The pad information is a pad information of BGA package, but it isn't user's PCB pad information.

Please check it.

Thanks and Best regards.
Glenn.

Hi,

Customers are considering "S25FL064LAB MFI010" as the boot ROM for the MCU.
The SPI clock output by the MCU is set to 24MHz.
Since the High width / Low width specification of the SPI clock of the MCU is "min.40%", the minimum width is (1/24) x 40% = 16.667ns.
On the other hand, the High width / Low width of the input clock on the NOR Flash side is "min.45%", so it is required  18.75ns.

Q1.
If I use an SPI clock with a frequency of 24MHz and a duty of ± 10% for the S25FL064L, does it work properly?
What happens if there is a problem?

Q2.
Is the duty ratio value "min.45%" of the SPI clock of  S25FL064L the same specification regardless of the oscillation frequency?

The maximum input frequency of this NOR Flash is 50MHz. The value of the fluctuation range (50% Psck-5%) for this frequency is considered to have the most severe effect on the NOR Flash setup / hold timing specifications.

Therefore, NOR Flash is designed to meet the timing specifications at 50MHz, so I think that the setup / hold margin is about twice as long as the clock at 24MHz.

Do you agree with my way of thinking?

Best Regards,

Naoaki Morimoto

I had an issue with the 4READ command.

Data is output one clock later than expected.

It seems that the change_addr signal is to blame: it fires depending on the ADS bit at 24 or32 bit boundary.

For commands configurable between 3/4 byte addresses this is correct, but i.m.o. 4READ always is 4 byte address,

so change_addr should always fire at32 bit boundary.

Please check whether assumption above is correct.

Regards,  Wim

My code mod to remove issue:

IF (current_state /= STANDBY) AND
    (Instruct /= WRR) AND (Instruct /= WRAR) THEN
 IF ((Instruct = READ) AND to_nat(WRR_reg_in) = 0) OR Instruct /= READ THEN
-- IF ADS = '1' AND address_cnt = 32 THEN
    IF address_cnt = 32 THEN
      change_addr <= '1', '0' AFTER 1 ns;
    ELSIF ADS = '0' AND address_cnt = 24 THEN
      change_addr <= '1', '0' AFTER 1 ns;
   END IF;
END IF;

PTNに基づき、後継品の評価において。

従来型格：S29GL064N90TFI030

Migraton to：S29GL064S70TFI030

EOL置換評価において、後継品は、書込みに3倍程度時間が掛かるとの指摘を受けました。

0.65nm（Automatic ECC)品においては、具体的に３倍かどうかは別にして、

従来より書込み時間がかかる、は回避できない事象でしょうか？

あるいは、回避アドバイスがありましたら、教えて下さい。

Hi,

the datasheet states an Erase Endurance of 1000 cycles and a Data Retention of 100 years after 10000 cycles.

Does that mean that the device can endure 10000 Program/Erase cycles without degradation or damage?

On what conditions is the limit of 1000 cycles based?

Thanks

We are using the Flash memory S25FL256SAGMFV01 in our system  for storing data logs , whenever we do sector erase we are facing the reset happening in the system,

kindly someone please provide help