Nor Flash Forum Discussions

Hello -- I'm currently trying to program the NVM device but am getting bad data when read back. 

For example:

- Executing a page programming command (PP) I am shifting in the PP command + 3 bytes of address (e.g. 24'h00_00_00)

- When I read the data back (READ command + 3 bytes of address) I get bad data on the device and also in the verilog simulation model I get X's. I have set the write enable latch before the program, and I can check that the 'Write in Progress' WIP bit is set as expected. I also wait until the WIP bit is deasserted to perform the read. 

- When I perform an erase command (e.g. CE) and then I perform a READ + 3 bytes of address, I successfully read back all 1's in the real-time hardware and in the verilog simulation model. I also set the write enable latch prior to an erase. 

Please help me understand if I am missing something to program the device. The device accepts other commands, including erase, but it programs bad data

Since S29GL032N90TFI040 was used, the 13th pin is used for NC.
Replacement product: Is it okay to use the 13th pin for NC in S29GL064S70TFI040?

Hai all,

I am working on STM32F769I-Discovery board with Nor-Flash memory (s25fl256l). Since it is a flash memory we need to make it  up in the U-boot level itself.  and I am using the u-boot version 2010-03. 

Can I get any u-boot level driver which compatible for STM32F769I-Disco board.

Thanks in advance.

Manjunath 

Hello,

I'm using S28HL512TFPBHI010 memory and I want to change sector architecture from hybrid to uniform. I tried to write new data to Configuration Register 3 (CFR3N[3] - UNHYSA - value 1) but when I read this register again it still has written old value: 0x00 (default). 

I checked my functions for register writing and for example I can change the interface by writting 0x41 to CFR5N and then read it by OCTOSPI inteface.

I read that writing to UNHYSA can be blocked by setting ASPO[1] - ASPPER bit to 0, but I read this register and it has got default value 0xFF - 1 = Persistent Protection Mode is disabled.

Is there anything else I should do to change sector oragnization?

Best Regards

We want to know how much the Sector Lock and Unlock timing is for S29GL032N NOR Flash.

Also please help us with status checking code/Pseudo code for completion of the above operation.

Regards,

Anil Patil

Hello!

           Now I want to use DDR transaction protocol (4S-4D-4D) with S25HS512T，and then how I would set the flash, which registers or pameraters should be configurated.

Hello I'm looking for a verilog simulation model for the S25FL064L Non-Volatile Memory device. I couldn't find it searching the Infineon website, but I'm not sure if that's because of the cypress merger. 

In our model library we actually have a verilog simulation model for a S25FL064P, which is originally a Spansion device. Note that I couldn't find either of them searching on the Infineon website so I am hoping that there is an archive of Spansion and/or Cypress verilog simulation models that is not part of the search. 

As a next request if the above cannot be found, is there a way to tell if the S25FL064L model would be equivalent to the S25FL064P model which we have? Based on the ordering information in the S25FL064L datasheet, the "L" is 'floating gate process technology' but "P" is not identified. 

Thanks 

Hello,
We are using this type of a memory in our board.
We are using it as SPI communication with CLK frequency 20 MHz.
We want to connect EEPROM SPI memory with the NOR Flash. The problem is the chosen EEPROM SPI memory runs at 10 MHz CLK. Is it possible to lower the frequency of the NOR FLASH to 10 MHz and to connect the EEPROM with the signals CLK, MOSI, MISO and two CS for both chips?
Thank you in advance!
Best regards,
Ana Ilieva