Nor Flash Forum Discussions
Hi all,
our board is equipped with a S70GL02GS 2Gbit NOR FLASH and a NXP T2080 processor.
We address two 256Mbyte physical banks (in this description I report the physical addresses we use ) divided in 4 128Mbyte logical banks connected to CS0 and CS2 as depicted in the following scheme:
CS2 Bank0 0xe0000000 -----------------------------------------------
128MByte
Bank1 0xe8000000 -----------------------------------------------
128MByte
CS0 Bank0 0xF0000000 -----------------------------------------------
128MByte
Bank1 0xF8000000 -----------------------------------------------
128Mbyte
----------------------------------------------- 0xffffffff (end of addressing)
On each bank we mount a filesystem (TFF0,TFF1,TFF2,TFFS3).
For CS0 we have TFF0 and TFF1, and each file system has a 64MByte dimension because these banks contain the reset word and the BootRom.
Our board boots (as written in the HW configuration of the T2080) from CS0 (thus from now on we will ignore CS2).
BootRom is written in the NOR memory starting from 0xfff00100 physical address and if we dump here we find the correct BootRom.
Here I attach the screenshot of the non corrupted memory:
see FIG1_not corrupted_NOR
When everything goes OK the micro T2080 boots correctly and the first instruction is found at the end of the bootRom. Thus at the address 0xfffffffC we find 0x4bff804.
On the other hand when the NOR flash is corrupted, the same part of the memory (size 131Kbyte = 0x20000) from address 0xFFFE0000 to address 0xFFFFFFFF, is erased (0xFFFF values written) as depicted in the following
see FIG2_corrupted_NOR
This fact (the deletion of the correct values in the physical address range 0xFFFE0000 + 0xFFFFFFFF of the NOR FLASH obtained by writing 0xFFFF in that address range) happens often.
Could be a spurious signal issue?
Could be a spurious signal on the reset input of the flash?
Coul be something else?
Thank you for your answers.
Massimo
Hi,
May I know the availability/life cycle of S29GL032N90BFA030 flash IC?
If it is no longer available ,could you please suggest an equivalent part for it along with the lead time.
Thanks
Show LessIs the S25FL127SABMFI100 different from the S25FL064LABMFI010 in terms of chip structure, package material, factory, etc.?
I couldn't find QTP, so I asked a question.
Show LessHello dear support,
Kindly ask you to help me with decoding date code for this part:
S25FL064LABMFI013
DC on package: 902JJ018
Also, if there is any user guide how to decode this by myself next time?
Waiting for your answer, thank in advance.
Show LessHello Team,
Issue: Reset pulse width of 1 microsecond is not working for new integrated flash (S29GL064S).
I have two flashes as below,
1. S29GL064N : In this flash we have use pulse width of 1 microsecond to reset flash and it works well, i.e., Flash gets restarted correctly.
2. S29GL064S : In this flash, we have same pulse width of 1 microsecond to reset flash, but here it does not work, i.e., Flash does not get restarted (it stucks). For testing purposes, we have provided 100 microseconds of pulse width and it works there.
Now my questions are:
1. What should be the exact pulse width to reset Flash and let Flash ready to start the system for both the Flash above.
2. Is there any difference between reset functionality for above mentioned flash? If yes, then please mentioned.
Show Less
Hi,
What is the absolute max operating junction temperature of S25HS512TFANHI01X?
Best Regards,
Kumada
Please check and advise temperature reflow range for below part.
Infineon MPN: S29JL064J55BHI000
Please send me the link to the document to download.
Thanks.
Show Less1) how to program multiple memory locations 0x0000 0000 --->0x0000 0001 --->0x0000 0002..... in one transaction in SDR QSPI .4S-4S-4S
2)then read in continuous manner with the help of mode with multiple memory locations QSPI SDR 4S-4S-4S
Show Less1.I'am reading the device id in 1s-1s-1s mode
2.enable 3 byte to 4byte by B7 cmd
4. reading all the registers values (status register 1-00h, status register 2-00h,cfgr register 1-00h,cfgr register 2-88h,cgfr register 3-00h,cfgr register 4- 08h) by 65 cmd with respective addresses(32 bits-1f in hexadecimal ) with read cycle of 8 bits .
5.enable write to volatile registers (cmd 50)
6.write enable cmd 71 with address and data , first iam writing in cfgr 1 -data 02 bit[ 1] should be high to enable 1-4-4 mode
7.write to volatile register 50 cmd
8.write enable cmd 71 with address and data , then iam writing in cfgr 2 -data E8 bit[ 6] and bit [5] should be high to enable 4-4-4 mode, this I'am writing in 1-4-4 format then its is convert to 4-4-4
9. after writing into all the registers i'am reading cfgr 1 ans cfgr 2 the values it showing is for cfgr 1-22 and for cfgr 2-33 that all are wrong values can you tell what is the issue i checked value for status register's also after write immediately it showed the value 02 means write is happening but i'am not getting where the issue is , that registes read and write in diff diff mode i have done that properly and also checked thrice?
see the attached pdf quer 2