Nor Flash Forum Discussions

Hi,

I am using the flash chip of CYPRESS,S25FL128SAGNFI000, but I have some questions that I don't understand  about the SDR AC Characteristics.

Question 1, At the 5.4 SDR AC Characteristics of the datasheet, Note 23/24/25, such as 23: Full VCC range (2.7 - 3.6V) and CL = 30 pF,

what't the meaning of the parameter "CL"?

Question 2, about the parameter of tv(Clock Low to Output Valid).

The datasheet says that the tv max value is 8.0ns when Note 23 happens.

but when the tv=8.0ns happens, about the SPI Single Bit Output Timing like Figure 32, it will happens like this:

Because the tv=8ns, so the time interval between CLK falling edge and rising edge must be greater than 8ns, so one period of CLK must be greater than 16ns.

So the CLK wil be less than 62.5MHz.

But for the single commands such as RDSR1, the SCK Clock Frequency can be 133MHz max.

So here is the question, according to the tv, the SCK frequency of single commands must be less than 62.5MHz, But according to the datasheet, the SCK frequency can be max 133MHz. I think there is contradictions between the two frequency.

Could help me to explain why this phenomenon happens?

Thank you so much and looking forward to your reply.

Problem.

The address of the documentation is http://www.cypress.com/file/448601/download page 96, an additional parameter for reading DLP, in DDR Quad I / O mode Read 4-byte Address. I do not understand the purpose of the DLP. Who gives the DLP, the purpose and application.

I need to run a fast read in the DDR Quad I / O Read 4-byte Address mode together with the stm32f7 chip.

The stm32f7 chip has hardware support for DDR Quad, with the mode of direct mapping of the address space (no separate reading functions are required). And also the mode of fast reading. This is when the instruction before the address is not sent, the chip is snapped to the place of this in read mode, and each call to the chip always occurs in read mode. Exiting this mode is the magic of reading a series of addresses in strict sequence.

I could not detect a similar mode for the S25FL256S chip. The instruction seriously slows down the speed of reading.

I am working on S25FS128S SPI. I don't get SPI response back from the Flash device. I use Single Bit Data mode.  CS, CLK, MTSR signals are good. I send RDID (0x9F/0x00/0x00/0x00). I don't receive 3 bytes of device id. MRST pin has no signal. It is my first time to work on the device. I am not sure if the device is in good condition or not. How can I verify that the device is in good condition? Are there some ways to identify whether the problem is from HW or SW?

Hello,

we have a strange problem with QSPI memories interfaced with a Renesas SH7266 microcontroller.

This microcontroller has an "On-chip rom boot" that allows booting on the serial flash, and copy 8K of this flash to its internal ram, and run the loaded code that is called "loader program".

This loader program can detect the location of the code of the application and copy it and run it in the internal ram of SH7266.

The application runs in the internal ram of the μP.

In most cases, it only read QSPI accesses, all blocks are write-locked.

However, it is sometimes necessary to store flash data. To do this, the application will first unlock the write accesses, write the necessary data and lock the write blocks again.

We note that the unlocking time of the blocks takes 200mS for 30μS of writing ...

The trouble is that if we turn off the power during the unlocking cycle (BP [0: 2] = 0) and turn on the power, the "on-chip rom boot" of the μP can no longer dialogue with the QSPI.

As if it remains in an unknown state.

The only way out of this incompatible state is to restart flash intialisation by the μP and its JTAG interface.

Once done, the system runs normally again without reprogramming the flash.

It seems that the QSPI remains in a state incompatible with the SH7266 boot chip despite the total power off (no hardware reset of available flash memory on the used package).

How can we avoid this problem?

We use a Cypress S25FL256S memory in a WSON8 (without RESET ...)

Thank you for your help

Eric F

Hi,

Is the first time I work with this SNOR, I think I send the correct SPI stream, but I have no data response from the memory yet.

The SNOR full model identification is: Cypress S25FL128SAGMFB013

Details on how it is currently configured and tested the SNOR:

1. Single Data Rate (SDR)
2. Mode 0: Clock Polarity (CPOL) = 0 and Clock Phase (CPHA) = 0
3. WP# / IO2 and HOLD# / IO3 and RESET# are left unconnected.
4. The SCLK operation frequency is: 25 KHz approximately.
5. The command that is currently tested is:

RDID = Read ID (JEDEC Manufacturer ID and JEDEC CFI) = 0x9F

1. The instruction bits are shifted into the device with the Most Significant Bits (MSB) first.
2. The time difference between the falling of CS# and the first CLK clock rising is 20 microseconds meets and exceeds the requirement:

t_TCSS=10 nanoseconds = CS# Active Setup Time (relative to SCK). This is the limit for the part type we are using: Single Die Package.

1. In the test setup there are at least 64 clock bits during the time the CS# is held low.

Here are the signals measured with an oscilloscope:

What do you think could be wrong in my SPI setup/sequence that is causing no response from the memory?