Nor Flash Forum Discussions
Hi,
Im trying to do a chip erase / bulk erase using C7 command . After which im trying to write and read register single register using write any register.
I ve attached the code snippet also for the same.its getting stuck in the chip erase point where the status returned a status of 0x3. kindly help with the issue and tell me whether the code approach is right.
uint8_t spi_flash_read_status_register (void)
{
uint8_t status, dummy_var;
ALLOW_TRANSFER;
PUSH(RDSR); // read status register command - 05
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(dummy_var); // discard one RxFIFO item
PUSH_ENQ(dummy_byte); // status register is returned during this
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(status); // read useful data
return (status);
}
void spi_flash_chip_erase(void)
{
uint8_t status, dummy_var;
ALLOW_TRANSFER; // if previous command has set EOQ
PUSH_ENQ(WREN); // write enable command
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(dummy_var); // discard one RxFIFO item
ALLOW_TRANSFER; // if previous command has set EOQ
PUSH_ENQ(CE); // Chip erase command - C7
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(dummy_var); // discard one RxFIFO item
do
{
status = spi_flash_read_status_register();
}
while (status & WIP); // wait here until chip erase is done.
}
void read _register(uint32_t address, uint8_t* p_data)
{
static uint8_t dummy_var;
uint8_t addr0, addr1, addr2 addr3;
addr0 = (uint8_t) (address & 0x000000FF);
addr1 = (uint8_t) ((address & 0x0000FF00) >> 8);
addr2 = (uint8_t) ((address & 0x00FF0000) >> 16);
addr3 = (uint8_t) ((address & 0xFF000000) >> 24);
ALLOW_TRANSFER; // if previous command has set EOQ
PUSH(READ_DATA); // read data bytes command
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(dummy_var);
PUSH(addr3); // most-significant byte of address
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(dummy_var);
PUSH(addr2); // middle high byte of address
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(dummy_var);
PUSH(addr1); // middle byte of address
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(dummy_var);
PUSH(addr0); // least-significant byte of address
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(dummy_var);
PUSH_ENQ(dummy_byte); // dummy bytes for generating CLK to slave
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(*p_data_bytes); // read useful data
}
void write_register(uint32_t address, uint8_t* p_data)
{
static uint8_t dummy_var;
uint8_t addr0, addr1, addr2,addr3;
addr0 = (uint8_t) (address & 0x000000FF);
addr1 = (uint8_t) ((address & 0x0000FF00) >> 8);
addr2 = (uint8_t) ((address & 0x00FF0000) >> 16);
addr3 = (uint8_t) ((address & 0xFF000000) >> 24);
PUSH_ENQ(WREN); // write enable command (must be done before every write !!!)
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(dummy_var);
ALLOW_TRANSFER; // from this point all following write to PUSHR will be sent
PUSH(WRITE_DATA); // read data bytes command - 0X65H
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(dummy_var);
PUSH(addr3); // most-significant byte of address
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(dummy_var);
PUSH(addr2); // middle high byte of address
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(dummy_var);
PUSH(addr1); // middle byte of address
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(dummy_var);
PUSH(addr0); // least-significant byte of address
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(dummy_var);
PUSH_ENQ(*p_data); // write data into the register
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
}
Regards,
Vignesh
Show LessIn my original design NOR flash PN: S25FL064LABMFM010 was installed then I replaced it with PN: S25FL064LABMFI013. I noticed that the device is working 1/2 the original speed. It is not stated in the datasheet that these 2 part numbers should perform differently. Am i missing something?
Show LessHi ,
Might we to adopt S25FL256LAGNFB010 for IS25LP256D-JLLE-TR cross reference part#?
Please advise us.
Kevin
Show LessHi ,
I'm developing code for accessing the flash for read and write using SPI .I'm using mpc5777c nxp chip to interface
with SPI nor flash. I need to program some data on the secured region
need to use secure region erase and secure region program. No need of password protection.
My doubt can this be done as normal sector erase 21h where we erase sectors of 4k bytes one by one from start address till the required address.
barring one change here only 1024 bytes can be erased and done as boundaries of 256 bytes(4 regions)
Same for programming also .similar to page programming but max 1024 bytes (as boundaries of 256 bytes).
Is my understanding correct?
Any examples for the same
Thanks in Advance
Vignesh.V
Show LessCan anyone tell me the difference between S29GL064N90FFIS20 and S29GL064N90FFI020
Hi,
FM28V020-TG; TSOP 32; datasheet shows pin orientation either on top left corner or on the middle, but on physical parts on right top corner. Please confirm correct pin orientation for these parts.
thank you,
Emelita
Show LessI recently migrated from the S25FL032P to the S25FL064L NOR Flash and during testing I realized that the Block Erase (64K Sector) command 0xD8 takes much longer than the original slower chip; the original flash, S25FL032P took about 6.5 seconds to erase 24 blocks 64K sectors while the newer flash, S25FL064L took over 8.5 seconds to complete the same task.
The S25FL064L should complete this task much faster than the S25FL032P according to the migration document and the datasheets.
Addition info:
The sector sizes are equal for both flash chips.
S25FL064L Block Erase Times (64KB physical sectors) – Typical Erase Time:450 Ms, Max Erase Time: 1150 Ms
S25FL032P Block Erase Times (64KB physical sectors) – Typical Erase Time:500 Ms, Max Erase Time :2000 Ms
What could cause the newer faster flash to perform slower than the older slower one?
Show LessHi all,
We got some trouble in linux(3.14.39 or 4.14.53) with S29GL01GS11TFIV10. Using command "hexdump -n 10 /dev/mtdblock0", we got incorrect data from S29GL01GS after linux bringing up (mtdblock0 is at NOR FLASH offset 0). Logic analyzer show that the address is correct but data is not. No file system mount, erase,program operated in the NOR FLASH during linux bring up. But hexdump again, correct data is got. Everything is working functionally except this issue. We tried a micron NOR FLASH, everything is ok.
Show LessLast year we switched to using the Cypress S29GL01GS10FHI02 Flash. We are currently having a problem on all these systems with erasing sector zero with our custom MTD driver running on a PPC 440EP. All other sectors erase and program fine using that driver. Sector zero can be erased and programed under U-boot. If U-boot is used to boot the system, then our custom MTD driver can erase and program sector 0 correctly.
When it fails to erase, the flash reports a status of A2 after ~10us, which according to document #001-98285 Rev R means Erase failure because sector is locked. However, the sector is not locked. It can be programmed with U-boot and the MTD driver in the same way after a U-boot boot. Also, reading the lock state (both volatile or not) of that sector returns 1 (Unprotected). Trying to unprotect the sector has no effect. The memory map appears to be correct as I can read the sector correctly from the MTD driver and all commands issued to the flash at that base address work (except the erase of sector zero). The bus speed is the same under U-boot or the factory boot (125ns). Nothing in the documentation hints at sector zero being special. The code to erase is very simple; the Sector address = base address in this case.
#define AMD_CMD_ERASE_START 0x0080
#define AMD_CMD_ERASE_SECTOR 0x0030
#define AMD_CMD_UNLOCK_START 0x00AA
#define AMD_CMD_UNLOCK_ACK 0x0055
#define AMD_ADDR_START 0x0555
#define AMD_ADDR_ACK 0x02AA
volatile u_short* base = (u_short*)( s->vaddr );
volatile u_short* addr = flash_make_addr (s, blkno);
*(base + AMD_ADDR_START ) = AMD_CMD_UNLOCK_START;
SYNC;
*( base + AMD_ADDR_ACK ) = AMD_CMD_UNLOCK_ACK;
SYNC;
*(base + AMD_ADDR_START ) = AMD_CMD_ERASE_START;
SYNC;
*(base + AMD_ADDR_START ) = AMD_CMD_UNLOCK_START;
SYNC;
*( base + AMD_ADDR_ACK ) = AMD_CMD_UNLOCK_ACK;
SYNC;
*( addr ) = AMD_CMD_ERASE_SECTOR;
SYNC;
Please help,
Frederic
Show LessI have a question regarding page programming when the data, sent along with PP command, exceeds the buffer size.
Here is the text from Cypress specification:
If more data is sent to the device than the space between the starting address and the page aligned end boundary, the data loading
sequence will wrap from the last byte in the page to the zero byte location of the same page and begin overwriting any data
in the page. The last page worth of data is programmed in the page. This is a result of the device being equipped
with a page program buffer that is only page size in length. If less than a page of data is sent to the device, these data bytes will be
programmed in sequence, starting at the provided address within the page, without having any affect on the other bytes of the same
page.
Let’s assume:
The buffer size is 256 bytes
Address is 0x0
Data received are 258 bytes (byte 0 is 0x00, byte 1 is 0x01, byte 2 is 0x02, …….. byte 255 is 0xFF, byte 256 is 0xAA, byte 257 is 0xBB)
After the receiving 256 bytes, the page buffer will contain: 0x00, 0x01, 0x02, ………, 0xFF
The new data (exceeding 256 bytes will overwrite the first byte): so the page buffer will contain at the end: 0xAA, 0xBB, 0x02, ………. 0xFF.
Now what data do you expect to be written to the memory?
Option A: Last 256 received bytes will be written to memory starting from the given program address which is 0x0 in this example
@address 0x0 à 0x02
@address 0x1 à 0x03
@address 0x2 à 0x04
…..
@address 0xFE à 0xAA
@address0xFF à 0xBB
Option B: The page program buffer is written to the corresponding memory’s page (page 0 in this example)
@address 0x0 à 0xAA
@address 0x1 à 0xBB
@address 0x2 à 0x02
…..
@address 0xFE à 0xFE
@address0xFF à 0xFF
Thanks,
Mona
Show Less