Nor Flash Forum Discussions
Now I have got product use S72XS256RE0AHBH2, but I have no driver code,so I unable know flash memory driver's behavior,
I just need to know something about S72XS256RE0AHBH2‘s internal state, What's the frequency erasing and how long each time?
It's not need to exactly, about is enough,
I only have Oscilloscope and Logic Analyzer, somebody could tell me how to know what's the frequency erasing and how long each time?
I would appreciate it very much if you could tell me!!
Show LessWhere can I get S72XS256RE0AHBH2's complete datasheet, I only found the datasheet of 7 pages
I've found a SPI NOR Cypress S25fs512s Verilog Model (https://www.cypress.com/verilog/s25fs512s-verilog ) and I get confuse: Spec says that
Read only bits are never modified and the related bits in the WRAR command data byte are ignored without setting a program or erase error indication (P_ERR or E_ERR in SR1V). Hence, the value of these bits in the WRAR data byte do not matter.
However in the model, I see that:
SR1_V[7] is SRWD bit, it is a Volatile copy of SRWD_NV and a Read only bit, but in above code, it is always updated with data programed by WRAR command. If there is a mistake here ?
Show LessPer the datasheet for the S25FL128S/S25FL256S family of devices, it appears that using a VIO of 3.3V results in better performance (higher throughput) than using a VIO of 1.8V. This sounds counterintuitive but I wanted to make sure this was correct before committing to a specific implementation in my design. Is there some internal circuitry that operations more effectively on 3.3V allowing the higher throughput (i.e. PLLs)?
Show LessThank you for your support.
Can you recommned to use the alcoholic solvent on 26KS512SDPBHV020 to remove flux?
Expected due date is 9th.May
Bset Regards,
Show LessHi,
I've been trying to fit the SpansionFS + BlockDriver + SLLD on a Cortex M0+ with 32kb of RAM and can't seem to make it fit. The .bss region is always about 50k over even when I reduce the Fat and Lim cache num to their minimum values.
What's the minimum size RAM needed to run the SpansionFS + Block Driver + SLLD?
Thanks!
Show LessHi all,
I'm using S25FL512SAGMFI011 for my bit stream storage with SPI interface operating @ 20MHz. I'm using CM3 to program the device, able to read idcode and status register correctly. so with the checking WEL and WIP bit i'm continuing to program, when ever WIP bit is "0" as stated in datasheet. But when i'm trying to read back using 0x03 it is giving all "0xFF". How can we sure that program is happened or happening other than WIP bit in status register?.
Can you guys please help me with this?
Thanks,
santosh koppaka@
Show LessI start using memory S25FL128L to replace ISSI one
problem when try to read ( normal read ) all parts show no problems at first use then by time some of them cannot be read by normal mode
then I added Mode bit reset command FFH prior to software reset 99H ,all parts works fine
so I want to know how memory enter high performance read mode without i issue any commands for that ??
is there any way to keep memory in stranded mode without worry about changing mode it self ?
Show Less