Nor Flash

1) Requesting the complete device specification data sheet for S25HL512TDPMHI010– not the ‘Device Overview’ sheet from the Cypress website

2) Is the product ID code and other programming information contained / detailed within the spec sheet? If not, can someone please provide the ID code?

Hi,

I'm trying to get the FAT FS implementation running on a system that contains the nRF52840 and the S25FS128S.

I can see that data is being written to the S25FS128S but I can't get beyond the writing and mounting of the file system. I am starting to suspect the issue might be with the non-uniform memory sector layout at the beginning of the flash memory.

I have the memory chip in 32bit addressing mode and I am trying to get it out of the standard hybrid sector mode with the following operation:

//test for non hybrid sectors
uint32_t reg_adr = 0x000004;
uint32_t status = 0;
uint32_t temp;

uint8_t location[5], rdBuf[2];

//location[0] = 0x06; /* Write enable. */
cinstr_cfg2.opcode = 0x06;
cinstr_cfg2.length = NRF_QSPI_CINSTR_LEN_1B;

status = nrf_drv_qspi_cinstr_xfer(&cinstr_cfg2, NULL, NULL);//CyU3PSpiTransferWords (location, 1, 0, 0);

rdBuf[0] = 0x8;

cinstr_cfg2.opcode = 0x71; /* Sector erase. */
cinstr_cfg2.length = NRF_QSPI_CINSTR_LEN_6B;
temp = reg_adr;

location[0] = (temp >> 16) & 0xFF;

location[1] = (temp >> 16) & 0xFF;

location[2] = (temp >> 😎 & 0xFF;

location[3] = temp & 0xFF;

location[4] = 0x08;


status = nrf_drv_qspi_cinstr_xfer(&cinstr_cfg2, location, NULL);//CyU3PSpiTransferWords (location, 5, 0, 0);

nrf_delay_ms(250);

So basically my question is two fold:

1. Is it possible that the hybrid sector layout is what is causing the issues with the FAT FS (It works perfectly well on the flash chip that comes with their development board)
2. Is the piece of code above the correct way to put the flash memory in uniform sector mode or am I missing any steps? (eg do I need to reset the chip after or something)

Thanks In advance,

Michiel

I have a S25FL128S/S25FL256S device, and I was going to leverage the 16 lowest address bytes from the OTP address space as a random number since it states:  (part 7.4 in https://www.cypress.com/file/448601/download)

“In the 32-byte region starting at address zero:

■ The 16 lowest address bytes are programmed by Cypress with a 128-bit random number. Only Cypress is able to program these bytes.

■ The next 4 higher address bytes (OTP Lock Bytes) are used to provide one bit per OTP region to permanently protect each

■ region from programming. The bytes are erased when shipped from Cypress. After an OTP region is programmed, it can be locked to prevent further programming, by programming the related protection bit in the OTP Lock Bytes.

■ The next higher 12 bytes of the lowest address region are Reserved for Future Use (RFU). The bits in these RFU bytes may be programmed by the host system but it must be understood that a future device may use those bits for protection of a larger OTP space. The bytes are erased when shipped from Cypress.”

However I was curious about the randomization, how can we ensure that each device is random.  Is there a possibility that a sequence can be determined.  Do you have any information regarding this?

Program Status bit, bit4 of Status Register, drives to 1 when Program fails. Is this flag set for any reason?

Is 1 set in Program status bit of Status register even when programming fails due to exceeding 100K of P/E Endurance?

I have a problem that I can program Status and Configuration Register using 0x01 command at the first time after the flash powered on, but when  I try to re-program the Register, the operation fails and Status Register value becomes 0x5F. Then I  I power on the flash again, the value Status and Configuration Register becomes all 0.

How many times can this Registers be programmed. I have programmed the Register about 200,000 times, is it because I have exhausted the use times.  Or it is because of some other reasons. 

Hi

Is there a "blank check" command for S70FLO1GS product?

If not, what is the simple and fastest way to do "erase verification" after bulk erasing?

thanks

Ely

FLASH: S25FL256S (Uniform 64KB sectors)

Hi,

I was trying to program my QSPI flash memory on my board.

However, it seems that the first 8 bytes in each bank (128Mb) of flash cannot be written.

The 0x00000000~0x00000007 and 0x01000000~0x01000007 always remains as 0xFF after erase, and cannot be programmed again.

Here is what i did:

1. Erase the whole chip using Bulk Erase Command. [Send: 0x60]

2. Perform a blank-check in 0x00000000~0x000000FF and 0x01000000~0x010000FF. [Read back, all the bytes are 0xFF]

3. Program 0x00000000~0x000000FF and 0x01000000~0x010000FF with an increased number serial (0x00~0xFF)

   [Send: 0x12      0x00 0x00 x00 0x00      0x00 ... 0xFF]

   [Send: 0x12      0x01 0x00 x00 0x00      0x00 ... 0xFF]

4. Read back. (The first 8 bytes cannot be written)

 0x00000000~0x0000100F: 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF  0x08 0x09 0x0A 0x0B ... 0xFD 0xFE 0xFF

 0x01000000~0x0100000F: 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF  0x08 0x09 0x0A 0x0B ... 0xFD 0xFE 0xFF

But when I try other addresses, such as 0x00000100~0x00000200, I can read exactly what I write.

How can I write the first 8 bytes in each bank of S25FL256S ?

THANKS!