Nor Flash Forum Discussions

Hello, Philip,

The S25FL512SAGxx as well as the S70FL01GSAGxx (65nM MirrorBit) are active Ordering Part Numbers

(OPN’s) and are currently in production.

In regards to the S25FL256LAGxx (65nM Floating Gate), this is the highest memory density, currently available.

The 512Mb and 1Gb memory density are not currently, available.

Do you have a more specific Ordering Part Number (OPN) Suffix for the S25FL512SAGxx and S70FL01GSAGxx?

Best regards,

Albert

Question regarding S25FL128S/S25FL256S flash devices with both VIO and VCC, and the treatment of CS#. The datasheet says that CS# must be pulled high during power up, ideally tracking VCC. But if VIO is at a lower voltage than VCC, (say VIO = 1V8) then wouldn’t pulling CS up to VCC violate the allowable VINH?

Suppose CS is pulled up to VIO, but VIO is powered up at a later time than VCC (say at some time after tpu) :. CS# does not follow VCC; will asserting RESET# after VIO comes up ensure that the device is properly initialized?

Hi Team,

Has Cypress S25FL512SAGMFMG10 been evaluated for Cycled HTOL(Erase cycle + HTOL) and Cycled RTOL(Erase cycle + RTOL) as defined in AEC-Q100-005?

If the evaluation has been performed, please provide the evaluation result data.

Thanks and tregards,

We have run into issues in the past when accessing the devices using 1-1-4 based reads and writes.  Cypress has a pullup on IO3 that is used to disable the HOLD# feature when in x1 mode but how strong is this pullup?

Our controller leaves IO2 and IO3 tristate when driving the command and address so if the previous read or write drives IO3 low, it depends on the pullup to reach an active high state.

Is there an alternate way to disable this feature?

我使用flash型号“W25Q128BV”读写其Device ID可以正常读出，但是使用贵司的S25FL064L读出来的ID都是0XFF。麻烦帮忙看一下这两个器件在读写的时候是否兼容或读写ID的区别是哪里？附件为W25Q128BV的数据手册

The ZYNQ 7000 only list compatibility with the S25FL-S part.

• Is the S25FL-L functionally compatible to the S25FL-S?
• Is there a pin equivalent part that I can migrate the S25FL256LAGNFM010 to the S25FL-S family?

Dear Cypress Experts,

I have several questions in the ASP PPB, please help have a check, thanks!

Question 1: Why can not program the PPB even when the PPBL Lock is 1

LONER_TESTS # sf probe 2:0

SF: Detected s25fl128s_64k with page size 256 Bytes, erase size 64 KiB, total 16 MiB

LONER_TESTS # sspi 2:0.0 32 9fffffff

00012018

#Read the PPBL Lock Bit

LONER_TESTS # sspi 2:0.0 16 A7

0001

LONER_TESTS # sspi 2:0.0 48 65800040

000000000001

#PPB Read (Still 0xFF)

LONER_TESTS # sspi 2:0.0 48 E2

0000000000FF

#WREN

LONER_TESTS # sspi 2:0.0 8 06

00

#PPB Program

LONER_TESTS # sspi 2:0.0 48 E300000000

000000000000

LONER_TESTS # sspi 2:0.0 48 65000000

000000000000

#PPB Read (Still 0xFF)

LONER_TESTS # sspi 2:0.0 48 E2

0000000000FF

LONER_TESTS #

Question 2: Why does the A6h seems not work?

#Read the PPBL Lock Bit

LONER_TESTS # sspi 2:0.0 16 A7

0001

#WREN

LONER_TESTS # sspi 2:0.0 8 06

00

#Clear the PPBL Lock Bit to 0

LONER_TESTS # sspi 2:0.0 16 A6

0000

LONER_TESTS # sspi 2:0.0 16 A7

0001

LONER_TESTS #

Question 3: How can I use the PPB to protect the lower 1M for this flash?

SF: Detected s25fl128s_64k with page size 256 Bytes, erase size 64 KiB, total 16 MiB

I'm looking for an IBIS model for the S70GL02GT12FHBV13 that supports 1.8V I/O operation. I found two models at this link http://https://www.cypress.com/search/all/S70GL02gt?sort_by=changed&f%5B0%5D=meta_type%3Asoftware_tools ,but they only support 3V (3.3V?) I/O. I used that model for simulating the address and control inputs (driven by a 1.8V driver), though I'm not sure the results are correct. However it does not help trying to simulate the S70GL02 driving the data bus. Is there another similar model that supports 1.8V operation that might be close?

Does the RESET of S29GL512T10TFI020 have schmitt trigger?

If not, are there any restrictions for rise/fall time?