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Nor Flash

New Contributor II


I am using the flash chips of CYPRESS, S25FL128SAGNFI000, and now I am doing the simulation of the QPP and QOR command.

But  there comes the result that didn't go as my desgin.

Would you tell me why this happened?

The details:

1, I have already programed the SR1 as [00H] and CR as [82H], which the latency cycles is 8, and Quad mode.

2, After power up the chip(in simulation), I writed the SR1 and CR, and read them, which is correct as the input, as the figure 1.

3, And then I read the 32 bits data of address 020000H, and the data would be FFFFFFFF, which is correct, as the figure 1.

4, Then I did the QPP command, and the address is 020000H too, and the write data is 12345678, and the SI/SO/HOLD/WP is correct, as the figure 2.

5, But then I did the QOR command, and the address is 020000H, and the read data is FFFFFFFF, which is not my input, as the figure 2

And I can't find why this happened, would you help me about that?

Here are the figures:





1 Solution


If the WIP bit is HIGH, it indicates two things -

  • Either the device has not completed the program operation. That is, the device is still busy. You should introduce a while loop after QPP command, such that you continuously keep reading the SR1 value and check the WIP bit, and leave the loop only when the WIP becomes LOW. After that, try reading the data using QOR command. I am providing a very rough structure for the while loop below.

          QPP command

          while ( WIP == 1)


               read SR1

               WIP = SR1 & 0x01


          QOR command

  • Or, some programming error has occurred, in which case P_ERR or E_ERR bit of the status register will be set (HIGH). In step 8, when you finally read the SR1 value after QPP command, what is the value of the P_ERR and E_ERR bits?

Meanwhile, I am also discussing your problem internally.

Thanks and Regards,


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