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xiaowei_li_3787
New Contributor II

Hi

I am using the flash chips of CYPRESS, S25FL128SAGNFI000, and now I am doing the simulation of the QPP and QOR command.

But  there comes the result that didn't go as my desgin.

Would you tell me why this happened?

The details:

1, I have already programed the SR1 as [00H] and CR as [82H], which the latency cycles is 8, and Quad mode.

2, After power up the chip(in simulation), I writed the SR1 and CR, and read them, which is correct as the input, as the figure 1.

3, And then I read the 32 bits data of address 020000H, and the data would be FFFFFFFF, which is correct, as the figure 1.

4, Then I did the QPP command, and the address is 020000H too, and the write data is 12345678, and the SI/SO/HOLD/WP is correct, as the figure 2.

5, But then I did the QOR command, and the address is 020000H, and the read data is FFFFFFFF, which is not my input, as the figure 2

And I can't find why this happened, would you help me about that?

Here are the figures:

1,

11091.PNG

2,

11092.PNG

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1 Solution
AS_36
Moderator
Moderator

Hi,

If the WIP bit is HIGH, it indicates two things -

  • Either the device has not completed the program operation. That is, the device is still busy. You should introduce a while loop after QPP command, such that you continuously keep reading the SR1 value and check the WIP bit, and leave the loop only when the WIP becomes LOW. After that, try reading the data using QOR command. I am providing a very rough structure for the while loop below.

          QPP command

          while ( WIP == 1)

          {

               read SR1

               WIP = SR1 & 0x01

          }

          QOR command

  • Or, some programming error has occurred, in which case P_ERR or E_ERR bit of the status register will be set (HIGH). In step 8, when you finally read the SR1 value after QPP command, what is the value of the P_ERR and E_ERR bits?

Meanwhile, I am also discussing your problem internally.

Thanks and Regards,

Apurva    

View solution in original post

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26 Replies
xiaowei_li_3787
New Contributor II

And I read the SR1 after QOR, there is no error message in the SR1 register.

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AS_36
Moderator
Moderator

Hi,

Can you explain why you have set the SR1 to 00h?

Setting the SR1 to 00h will make the Write Enable Latch (SR1 [1]) to zero. If you go to the datasheet of S25FL128S (link - http://www.cypress.com/file/448601/download), under section '9.5.3 Quad Page Program' on page 100, it says - "A Write Enable command must be executed before the device will accept the QPP command (Status Register 1, WEL=1)."

Thanks and Regards,

Apurva

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xiaowei_li_3787
New Contributor II

Hi

Thank you for your reply.

About the SR1, I just want to initialize the SR1 register at the begining of all the operation.

But I knew that I lost the WREN command at the QPP command...

And I have add the WREN command before the QPP command.

But there is still something wrong..

1, I have input the WREN command and the WEL is high. And then I input the QPP command and the four signals may be OK for the chip.

11093.PNG

2, But then I input the QOR command, and read the same address, but the output data is all 'Z'.

3, And then I input the WRSR1 command and found that the WEL is high, the WIP is high too.

Is this means that ont of the commands before may be not over?

11094.PNG

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AS_36
Moderator
Moderator

Hi,

In the 3rd point, I suppose you mean you are sending the RDSR1 command?

If the WIP is HIGH, yes, it indicates that the QPP command has not completed execution.

You could try polling the WIP bit of the SR1, after sending the QPP command. When the WIP becomes zero, it will indicate the successful completion of the process. After that, you can send QOR, and check the value.

Thanks and Regards,

Apurva  

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xiaowei_li_3787
New Contributor II

Hi

Thank you so much for you help.

1, Do you means that set the WIP high through the WRR command?

(The 7.5.1 of datasheet says about WIP: While WIP is 1, only Read Status (RDSR1 or RDSR2), Erase Suspend (ERSP), Program Suspend (PGSP), Clear Status Register (CLSR), and Software Reset (RESET) commands may be accepted.)

2, I do the simulation again, After the QPP command , I read the SR1 status , SR1's WEL and WIP is high, which means the flash is busy...

I think that the QPP command may not be executed right...

but I think I do the same timing as the datasheet...

Is there any way that can find which part is not OK?

11095.PNG

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xiaowei_li_3787
New Contributor II

Or Is there some timing requirement about QPP command?

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AS_36
Moderator
Moderator

Hi,

  1. No. The WIP bit is a Read Only bit, it set HIGH/LOW internally. You are not supposed to set it by WRR command. By the term 'polling', I mean you can continuously read the SR1 register to check the status of the WIP bit. When it becomes LOW, it will indicate that the process has completed.
  2. Regarding the time requirement of QPP command, I will discuss internally and let you know shortly.

Thanks and Regards,

Apurva

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AS_36
Moderator
Moderator

Hi,

There is no specific timing requirement for QPP command.

Thanks and Regards,

Apurva

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xiaowei_li_3787
New Contributor II

Hi,

Thank you very much for your help!

But I am still puzzled about this question..

1, About the WIP, which is SR1[0], I know it is a read only bit, and although I writed the SR1 value through the WRR command, but I just wanted to use the WRR to write CR register, and the SR1 value writed by me is 00H, which is the same as the the device first shipped from Cypress to the customer. So, I think is wouldn't matter to the result.

2, About the figure of the answer by me(2018 11:45 PM), After the WREN and QPP, I think the data should be input to the chip correctly, but after QPP, I read the SR1 register, it shows that the SR1's WEL and WIP is high, which means the flash is busy...which meads that the QPP command may not be executed right...

But I can not figure out which part is not right...

Would you help me about that?

Or is there any way that I can use to find which part is wrong?

Thanks again.

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xiaowei_li_3787
New Contributor II

Hi,

I have done some other tests to find the reasons, but sorry that I still can't find what is wrong...

Now the command order is as follows:

1, Power up the chip(start the simulation) and wait for 300us

2, Do the WRR command and set the SR1 as [00H], CR1[82H](latency code is 10 and quad bit is 1), and wait for 500ms to make sure the registers have been rewrite correctly.

3, Do the RDSR1 and RDCR command, and the SR1 is [00H], the CR1 is [82H], which is correct.

4, Do the QOR command(address is 020000H) and just read 32bits, and the output of IO0-IO3 is all 1, which means the 32 bits data from  020000H is FFFFFFFF, which is correct.

5, Do the RDSR1 command, and the SR1 output is [00H], which doesn't show any error message.

6, Do the WREN command and do the RDSR1 command, and the WEL bit is 1, which means it is ready to do the QPP command.

7, Do the QPP command , input the 32H and 020000H address and the 32bits write data in sequence.

8, Do the RDSR1 command, and I found that the WEL and WIP bit of SR1 are all '1', which means the QPP command is not executed correctly. But I did the check as the datasheet, and I couldn't find where is wrong...

It is king of emergency, .Please help me ....Thank you  very much...

Here are the simulation pictures:

1, QOR and RDSR1

11131.PNG

2,  WREN and RDSR1 and QPP

11132.PNG

3, QPP and RDSR1, RDSR1's output is wrong..

11134.PNG

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AS_36
Moderator
Moderator

Hi,

If the WIP bit is HIGH, it indicates two things -

  • Either the device has not completed the program operation. That is, the device is still busy. You should introduce a while loop after QPP command, such that you continuously keep reading the SR1 value and check the WIP bit, and leave the loop only when the WIP becomes LOW. After that, try reading the data using QOR command. I am providing a very rough structure for the while loop below.

          QPP command

          while ( WIP == 1)

          {

               read SR1

               WIP = SR1 & 0x01

          }

          QOR command

  • Or, some programming error has occurred, in which case P_ERR or E_ERR bit of the status register will be set (HIGH). In step 8, when you finally read the SR1 value after QPP command, what is the value of the P_ERR and E_ERR bits?

Meanwhile, I am also discussing your problem internally.

Thanks and Regards,

Apurva    

View solution in original post

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xiaowei_li_3787
New Contributor II

Hi

Thank you so much for your help!

1, I will do the test that read the SR1 continuously right now.

2, the SR1 value that read back is [0000_0011], only the WEL and the WIP is high, and there are no error messages

Thank you so much for helping me , and I have another question that I think may be related to this problem.

In the simulation model of S25fl128s(S25fl128s.zip), there is a model source of the chip named testbench_s25fl128s_vhdl.vhd.

there are some codes like this :

11135.PNG

And the Paremeter of tdevice_BP(I can't find this tBP meaning in the chip datasheet), the note says it is the typical byte programming time , what does this means ?

Does it mean that I should wait for this long time after I do the byte program every time?

And it is in the simulation file, what is the situation in the real chip ?

Thanks again!

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AS_36
Moderator
Moderator

Hi,

Can you answer the below two questions -

  • Can you please check and tell us why the frequency of QPP is slower than that of WREN/QOR?

11093.PNG

  • According to the datasheet, there should have been 8 dummy cycles for QOR command, but there don't seem to be 8 dummy cycles on the QOR waveform

1234.png

You can also try using our sLLD package (http://www.cypress.com/documentation/software-and-drivers/low-level-driver-spi-flash​).

It has existing APIs for QPP and QOR which includes the polling and WREN operation internally.

Thanks and Regards,

Apurva

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xiaowei_li_3787
New Contributor II

Hi Thank you so much for your help!

Here are the answers:

1,Can you please check and tell us why the frequency of QPP is slower than that of WREN/QOR?

---->As the datasheet says, the maximum frequency of QPP is 80MHz, so I choose 50MHz as my QPP frequency.(My Flash module's system clock is 200MHz, the QPP clock of SCK is made by myself), and I choose 100MHz as my QOR frequency(which the maximum frequency is 104MHz).

And the most important reason of the different frequency is that I want to use the QPP and QOR to get a fastest program/read speed...

So...

Will there be some problem about the different frequency?

2,According to the datasheet, there should have been 8 dummy cycles for QOR command, but there don't seem to be 8 dummy cycles on the QOR waveform

----> I am so sorry that the figure can't be seen clearly.

There are the 8 dummy cycles in the command consequence, as is lined out as red line.(DUMMY/8clk).

Because I set the IO0-IO3 as a high impedance in the dummy cycles, so the IO0-IO3 look blue in the figure.

And Because the QOR output is wrong, so they just all line together as  blue...

11141.PNG

===========================================================================================

And I did the test as your advice yesterday. And I did find something strange.

According to the reply by me at 2018 10:11 PM, I think the parameter of tBP is one of the most important reason of this question.

1, Meaning of tBP

In the simulation model of S25fl128s(S25fl128s.zip), there is a model source of the chip named testbench_s25fl128s_vhdl.vhd.

there are some codes like this :

11135.PNG

And the Paremeter of tdevice_BP(I can't find this tBP meaning in the chip datasheet), the note says it is the typical byte programming time , what does this means ?

Does it mean that I should wait for this long time after I do the byte program every time?

And it is in the simulation file, what is the situation in the real chip ?

2, Test result

The WEL and WIP are high after I do the QPP command, and the WEL and WIP will be down to 0 until about 550us after the QPP command.

just like the pictures.

I think this is related to the tBP in the question (1) , but the 550us is kind of different of the tBP.

So I am confused again...

11136.PNG

11137.PNG

And I will do some more simulations to test the QPP and QOR together.

Thanks.

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AS_36
Moderator
Moderator

Hi,

  1. Regarding the meaning of tBP, I am discussing this internally with our product experts and shall let you know shortly.
  2. Now that WIP and WEL are becoming LOW, can you please verify the data that you have programmed by reading using QOR command?

Thanks and Regards,

Apurva

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xiaowei_li_3787
New Contributor II

Hi, Thank you for your help!

As you said, I waited about 550us after QPP command, and then I read the SR1 again, the value of SR1 is [00H], so I think it meant that the commands before had been executed correctly.

And then I writed the QOR command, and read the same address as QPP, the outputs of IO0-IO3 were right, which is 12345678 as the QPP command' input data.

So, I think if I do the QOR command after 550us(tBP), it will be right..

But now the problem is tBP, Does it mean that I should wait for this long time after I do the byte program every time?

And it is in the simulation file, what is the situation in the real chip ?

Thank you so much for your help, it really helped me a lot..

11142.PNG

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AS_36
Moderator
Moderator

Hi,

Congratulations on being able to read the correct data after QOR.

Regarding the significance of tBP, please give me a little more time to discuss it internally.

Rather than waiting for a particular time period after a program operation, it is always better to poll the SR1 value to check the status of WIP bit, because sometimes it may happen that an operation might take longer/lesser time as compared to the stipulated time in the datasheets.

Thanks and Regards,

Apurva

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xiaowei_li_3787
New Contributor II

Hi, A

I really appreciate your help!

As what you said, is this the better way to do the QPP command :

1,first input the QPP command and the address and the QPP data in sequence.

2,After the last bit input the chip, pull up the CS#, and then pull down the CS# and input the RDSR1 command, and again and again untill the SR1 output is [00H].  (Is there some timing requirements between the CS# high and down?)

3, When the SR1 is [00H], then other commands can be input again..

And I am looking forward to your reply about tBP ~~

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AS_36
Moderator
Moderator

Hi,

Your 1st step is correct. Send the QPP command, address and QPP data as it is.

Pull the CS# HIGH. You can give a delay of 100ms here.

Pull the CS# LOW again. Send the RDSR1 command and store the SR1 value in a variable (say 'sr'). Instead of comparing sr with 00h, you should perform AND operation between sr and 0x01, and store the result in another variable (say 'wip'). Pull the CS# HIGH.

This variable wip will now indicate the status of WIP bit solely. You can run the while loop using this wip variable.

You should not compare SR1 with 00h because Status Register is a combination of several bits, and if you use functions like Block Protection, all bits of the Status Register might not be zero at all times.

Thanks and Regards,

Apurva

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xiaowei_li_3787
New Contributor II

Hi A,

Thank you for your reply~

About the CS# from low to another low, "You can give a delay of 100ms here",

In the datasheet of 5.4 SDR AC Characteristics, it says,

tCS

CS# High Time (Read Instructions)  10 ns

CS# High Time (Program/Erase)  50ns

Does the tCS mean that the CS# should behold this time between two commands?

(I think the 100ms may be too long for my design module...so, I want to know the min time...)

Thanks again!

L.

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AS_36
Moderator
Moderator

Hi,

Yes. tCS is the minimum time for which the CS# should remain HIGH after a Read or Program/Erase operation.

You can follow the specifications mentioned in the datasheet. 

Regarding tBP, it is some carryover parameter from the legacy platform, it is of no use on FL-S flash.

The Verilog model on the website shall be updated.

Thanks and Regards,

Apurva

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xiaowei_li_3787
New Contributor II

Hi A,

Thank you for your help!

I am so sorry to bother you for so many questions...

1, About the tBP, since it is of no use on FL-S flash chip, does it mean that I can do the QOR command immediately after QPP command + tcs?

2, In the datasheet, there is a tPP,Page Programming (256 bytes), 250 750 us.(9.10).

I think it means that the time between the first byte writed into the flash to the page program finished.

Is this right?

Or It means that the time between page program done and CS high to the WIP='0'?

Should I wait for some time after page program?

(Sorry that I havn't received my real circuit board and I can't do the real test..)

Thanks again.

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AS_36
Moderator
Moderator

Hi,

1. Though tBP is not in relation to FL-S, you should still poll the WIP bit after QPP command to check the device status, and once WIP becomes LOW only then you should send the QOR command. tCS is the amount of time for which you should wait between one CS# HIGH and LOW.

2. The QPP command will begin execution only when the CS# is made HIGH. So tPP is the time period between CS# HIGH and WIP LOW.

Instead of waiting for a particular time period, it is always better to poll the WIP bit to check its status. Is there any specific reason why you are insisting on waiting rather than polling the bit?

Thanks and Regards,

Apurva

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xiaowei_li_3787
New Contributor II

Hi A,

Thank you so much for your patient explanation.

1, I understand the way of poll the WIP to execute the next command.

2, About waiting and polling, there are indeed some reasons.

This time, the development of Cypress Flash is as a part of an upgraded project, and the last version of the project used a parallel flash chip.

Besides, there are a lot of the commands related to the upper module, so the speed of QPP command and QOR command(or the time that QPP and QOR need ) is kind of something important to me.

So I want to confirm the actual time that these commands need, and it would really helps me to correct the design about flash now.

So, is there any way to confirm the time that QPP(when program different number of bytes) need?

Looking forwards to your reply~~~

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AS_36
Moderator
Moderator

Hi,

Unfortunately we do not have the data for QPP time for different number of bytes.

The datasheet mentions the typical and maximum values for tPP. If you want to wait, you can follow that spec in the datasheet.

But, if you choose to wait after QPP, instead of polling the SR1, you will not be able to know if a programming error has occurred. (P_ERR bit of SR1 indicates if programming error has occurred).

Thanks and Regards,

Apurva

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xiaowei_li_3787
New Contributor II

Hi A,

Thank you so much for your help!

I understand what you suggested, and I think I should use the way of polling the SR1 between the different commands.

I think my questions about all these details are clear.

I don't know how to thank you but you really helped me a lot

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