Sporadic and Silent Sector Erase Failure [S25FL512S NOR Flash]

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vishy
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I am interfacing the S25FL512S NOR Flash memory with the STM32f4 microcontroller. I have written my own device driver implementation, supporting the FAST_READ (0x0C), PROGRAM (0x12), and SECTOR_ERASE (0xDC) commands.

All of the three commands have been demonstrated to work. However, SECTOR_ERASE command would successfully erase the sector only about 50% of the time in the current estimation.  

The biggest issue is the fact that when the SECTOR_ERASE command fails, it fails silently, without raising the E_ERR flag in the SR1 register. That means that there is no way to differentiate between the successful SECTOR_ERASE and non-successful SECTOR_ERASE without reading the whole sector and checking if all the byte locations equal to 0xFF.

To show precisely how this silent failure looks like, I am providing you with a screenshot (2 parts, since the signal capture was too long to fit into one) of the signals (captured with a logic analyzer) during the execution of the sector erase sequence. The sequence for erasing the sector is the following:

- RDSR1
- WREN
- RDSR1
- SECTOR_ERASE
- Issue RDSR1 and continuously check if WIP is deasserted

sector_erase_failure_part1.PNG

sector_erase_failure_part2.PNG

 One peculiar thing that stands out each time when SECTOR_ERASE fails is that, the first RDSR1 command (issued directly after SECTOR_ERASE) returns 0xFF, and only the second RDSR1 command returns 0x03 (WEL and WIP bits asserted). After a few RDSR1 commands, the value returned is 0x00, which suggests successful sector erase has been performed. However, after reading the sector, it is obvious that it has not been erased. Also, RDSR1 returns 0x00 only a milisecond or so after the SECTOR_ERASE has been issued, which automatically suggests there is something wrong since SECTOR_ERASE normally takes a few hundred miliseconds to erase the whole sector.

Normally, SECTOR_ERASE is successful every time after power-on-reset. However, it usually fails every second time or so for erasing the same sector after that.

My configuration register is always set to 0xC0 (only latency bits set to 11, indicating that there is no need for the dummy cycles during fast read command). SR1 register is configured to 0x00.

Could you please provide me with any hints of why could this be happening?

Thank you for your time.

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1 Solution

Hello

From the  trace, the first SR read delivers 0xFF as if the command was somehow ignored and the status register was not really read.

At this point, we are suspecting a signal integrity issue where spikes or unclean clock or IO signals may cause commands to be ignored.

For instance, we see some irregularities on the  clock signal itself where the clock high time and low time are very different. Allowed here is a max discrepancy of 10% not more, e.g: clock low time resp. clock high time should be in the range of [45% - 55%] of the whole clock period.

Thank you

Regards,

Bushra

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