Customers are considering "S25FL064LAB MFI010" as the boot ROM for the MCU.
The SPI clock output by the MCU is set to 24MHz.
Since the High width / Low width specification of the SPI clock of the MCU is "min.40%", the minimum width is (1/24) x 40% = 16.667ns.
On the other hand, the High width / Low width of the input clock on the NOR Flash side is "min.45%", so it is required 18.75ns.
If I use an SPI clock with a frequency of 24MHz and a duty of ± 10% for the S25FL064L, does it work properly?
What happens if there is a problem?
Is the duty ratio value "min.45%" of the SPI clock of S25FL064L the same specification regardless of the oscillation frequency?
The maximum input frequency of this NOR Flash is 50MHz. The value of the fluctuation range (50% Psck-5%) for this frequency is considered to have the most severe effect on the NOR Flash setup / hold timing specifications.
Therefore, NOR Flash is designed to meet the timing specifications at 50MHz, so I think that the setup / hold margin is about twice as long as the clock at 24MHz.
Do you agree with my way of thinking?
Hi Morimoto san,
I have discussed this question internally with product experts and they would like to know more about the customer application before answering. Could you please tell me the customer name and application?
The customer name is not disclosed.
The application is transportation and NOR Flash is used for SH2A booting.