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Anonymous
Not applicable

Hi,

I'm planning to use the S70FL01GSAGBHIC10 QSPI for Zynq configuration.  Since this part is a dual stacked 512Mb chip, it contains two chip selects.  I can connect these two chip selects to the Zynq MIO pins 0/1.  Should I connect the data lines from MIO2-MIO5 to MIO10-MIO13 and also to the QSPI?  Also, there are two clocks provided from the Zynq to run two separate QSPI chips.  Should I OR the two clocks together to connect to the single clock input on the QSPI?  Lastly, do the chip select signals on the QSPI require pull-ups or are there internal pull-ups on these signals?

Thanks for any help.

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1 Solution
TakahiroK_16
Employee

Hello,

With the S70FL01GS, you can configure Zynq QSPI as the "Dual SS, 4-bit Stacked I/O" which described in the Xilinx's document (UG585). In this configuration, you should connect MIO0/1 to two chip selects, MIO2-MIO5(QSPI0 IO0-3), and MIO6(QSPI0 CLK). MIO9(QSPI1 CLK) and MIO10-MIO13 (QSPI1 IO0-3) are not used.  There is no internal pull-ups on the Chip Selects in the FL01GS so please place external pull-ups.

Best Regards,

Takahiro

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4 Replies
BushraH_91
Moderator
Moderator

Hello Bj,

Thank you for contacting Cypress Community Forum. We have received your inquiry and currently reviewing the issue. We will get back to you as soon as we find the resolution.

Have a wonderful day

Regards,

Bushra

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TakahiroK_16
Employee

Hello,

With the S70FL01GS, you can configure Zynq QSPI as the "Dual SS, 4-bit Stacked I/O" which described in the Xilinx's document (UG585). In this configuration, you should connect MIO0/1 to two chip selects, MIO2-MIO5(QSPI0 IO0-3), and MIO6(QSPI0 CLK). MIO9(QSPI1 CLK) and MIO10-MIO13 (QSPI1 IO0-3) are not used.  There is no internal pull-ups on the Chip Selects in the FL01GS so please place external pull-ups.

Best Regards,

Takahiro

View solution in original post

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DaFi_1319201
New Contributor

Hello,

Can you advise how to connect two S70FL01GS devices to a Zync  UltraScale+ MPSOC (ZU09EG) device?

I would like to have a total flash storage of 512MB.

Thank you,

Dave

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TakahiroK_16
Employee

Hello Dave,

The QSPI controller in the Zynq MPSoC has two chip selects and they are used for one S70FL01GS. Therefore, you cannot connect two S70FL01GS to the Zynq MPSoC QSPI controller without external chip select multiplexer.

The Zynq MPSoC also has SPI controller (Quad operation is not supported) that can support up to six chip selects depending on your MIO settings.

Another option is to integrate QSPI controller IP (like AXI Quad SPI core from Xilinx) into FPGA side of the Zynq MPSoC.

Thanks,

Takahiro

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