S29JL064J Sector Erase & Chip Erase's flow chart and Data# Polling Algorithm

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yuxi_3250341
Level 3
Level 3
First like received

Hi there,

In the S29JL064J datasheet (Document Number: 002-00856 Rev. *I) on page 31 Figure 7 is a flow diagram for Sector Erase and Chip Erase operations:

pastedImage_1.png

Also, on page 35 there's the Figure 8. Data# Polling Algorithm:

pastedImage_2.png

From my previous discussions with Cypress technical support friends (thread: For NOR Flash, can RY/BY# (or Ready/Busy) pin replace Data Polling (and toggling bits) method? ), in my understanding, if I'm NOT doing erase suspend and only erase ONE SECTOR in a erase comand sequence, then polling DQ7 and DQ5 and run though the forthmentioned "Data# Polling Algorithm" shold be sufficient to know the result of a Sector Erase or Chip Erase operation: DQ7 tells me whether it's finished and DQ5 tells me whether it's successful or fail.

So, my questions are:

1, Am I correct in the above understanding?

2, In order to know the result of a Sector Erase or Chip Erase operation, is the above Figure 8 "Data# Polling Algorithm" flowchart sufficient? Is it OK that I DO NOT use the above Figure 7 "Erase Operations" flowchart?

3, Reversely, in order to know the result of a Sector/Chip Erase op, can I ONLY use Figure 7 "Erase Operations" flowchart and DO NOT use Figure 8 "Data# Polling Algorithm" flowchart?

4, As of the answers to the previous questions 1 thru 3, does these answers also apply to Cypress NOR devices including S29JL064H, S29JL064J, S29GL256P and S29gl01GT?

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1 Solution
Apurva_S
Moderator
Moderator
Moderator
100 likes received 500 replies posted 250 solutions authored

Hi,

Thank you for contacting Cypress Semiconductor.

  1. I would like to clarify that DQ7 and DQ5 bits both remain LOW during an erase operation. According to the flowchart in figure 8 we need to continuously keep polling the two bits (DQ7 and DQ5). If the DQ7 bit goes HIGH it indicates a successful completion of the erase operation and data polling can be stopped. In a certain scenario it may happen that both DQ7 and DQ5 change states at the same time and DQ7 is read as LOW and DQ5 (which is being read after DQ7) reads as HIGH. This is considered as an error condition. In such a case, DQ7 and DQ5 bits should be read again to confirm. If DQ7 remains as LOW and DQ5 as HIGH then the erase operation was unsuccessful and if both are read as HIGH then erase operation can be concluded as successful. (Please see foot note 29 on page 35 of the datasheet)
  2. Figure 8 is just an expansion of block number 3 "Data Poll to Erasing Bank from System" from Figure 7.
  3. Figure 8 is just an expansion of block number 3 "Data Poll to Erasing Bank from System" from Figure 7.
  4. All of our parallel NOR flash devices have similar data# polling algorithm. I request you to refer the respective datasheets for specific details.

i would like to recommend you to use our Low Level driver for Parallel NOR Flash devices. You can download the driver from here.

Best Regards,

Apurva

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4 Replies
Apurva_S
Moderator
Moderator
Moderator
100 likes received 500 replies posted 250 solutions authored

Hi,

Thank you for contacting Cypress Semiconductor.

  1. I would like to clarify that DQ7 and DQ5 bits both remain LOW during an erase operation. According to the flowchart in figure 8 we need to continuously keep polling the two bits (DQ7 and DQ5). If the DQ7 bit goes HIGH it indicates a successful completion of the erase operation and data polling can be stopped. In a certain scenario it may happen that both DQ7 and DQ5 change states at the same time and DQ7 is read as LOW and DQ5 (which is being read after DQ7) reads as HIGH. This is considered as an error condition. In such a case, DQ7 and DQ5 bits should be read again to confirm. If DQ7 remains as LOW and DQ5 as HIGH then the erase operation was unsuccessful and if both are read as HIGH then erase operation can be concluded as successful. (Please see foot note 29 on page 35 of the datasheet)
  2. Figure 8 is just an expansion of block number 3 "Data Poll to Erasing Bank from System" from Figure 7.
  3. Figure 8 is just an expansion of block number 3 "Data Poll to Erasing Bank from System" from Figure 7.
  4. All of our parallel NOR flash devices have similar data# polling algorithm. I request you to refer the respective datasheets for specific details.

i would like to recommend you to use our Low Level driver for Parallel NOR Flash devices. You can download the driver from here.

Best Regards,

Apurva

Hello Apurva,

Thank you for your careful and detailed explanations!

As you mentioned, Figure 8 is just an expansion of block number 3 "Data Poll to Erasing Bank from System" from Figure 7 -- My further question is, if I view Figure 8 as block number 3 in Figure 7, then it means after Figure 8's flowchart gives me "PASS", I still have to do the "Data = FF?" check which is defined in Figure 7 -- however, I think such "Data = FF?" check is unnecessary, because from Figure 8's DQ7 and DQ5 I already know that the erase is finished and successful, and such "Data = FF?" check seems redundant and unnecessary.

Am I right?

Why do the "Data = FF?" check? Is it a must? Can I skip and jump over it?

Thanks & BR

xieyl

200228

Hi Xieyl,

Yes, you are right. Checking "Data = FF?" is not a must after data polling and can be skipped.

Best Regards,

Apurva

Hi Apurva, thank you for explanations and clarifications!

Thx & BR~

xieyl

Feb 28, 2020