S29JL064H Timing error: tGHVL hold violatin

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yuxi_3250341
Level 3
Level 3
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Hi there,

While I am using Cypress S29JL064H Verilog simulation model to do behavioral simulation, the sim log gives a weird timing Error:

  # ** Error: ../vrf/S29jl064h/model/s29jl064h.v(1161): $hold( posedge OENeg:1000951 ns, CENeg:1000951 ns, 1 ns );

  #    Time: 1000951 ns  Iteration: 1  Instance: /tb_norc/U_064H

Follow this error, line 1161 in <s29jl064h.v> is:

  $hold (posedge OENeg, CENeg , thold_WENeg_OENeg, Viol);

And, the comments of "thold_WENeg_OENeg" says "tGHVL edge /".

In my simulation waveform, at the specified time (1000951 ns), the OE# rising edge and OE# rising occurs at exactly the same time. However, it seems the $hold requirement in the model requires that CE# rising edge should be later than posedge OE#, and seems this is defined by "tGHVL" parameter.

I went through the datasheets of S29JL064H, S29JL064J, S29GL256P and S29GL01GT, and there is NOT such an AC parameter called "tGHVL", and I CANNOT find any spec requiring that CE# rising edge should be later than posedge OE#.

Where can I find the definition of "tGHVL"?

Can I ignore the forthmentioned timing Error issued by the S29JL064H Verilog simulation model?

Or, should I modify my design to ensure that no timing error is reported?

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1 Solution

Hi xieyl,

I would like to inform you that our behavioral models are timing accurate and need SDF to work correctly.

Best Regards,

Apurva

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6 Replies
Apurva_S
Moderator
Moderator
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100 likes received 500 replies posted 250 solutions authored

Hi yuanlu xie,

Thank you for contacting Cypress Semiconductor.

I would like to know whether you are running the simulations with SDF or not?

Best Regards,

Apurva

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Thanks Apurva,

I'm currengly doing behavioral simulation and no SDF file is used.

Thanks & Best Regards.

xieyl

March 06, 2020

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Hi xieyl,

I would like to request you to use SDF file.

Best Regards,

Apurva

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Hi Apurva,

Are you saying that, even if I am simply doing behavioral simulation (or call it functional simulation), I still have to use SDF file together with the model.v Verilog code?

In my knowledge, if I use SDF file then it is no longer behavioral sim, but timing simulation. Why should I include SDF in behavioral sim?

Thanks & Best Regards

xieyl

200309

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Hi xieyl,

I would like to inform you that our behavioral models are timing accurate and need SDF to work correctly.

Best Regards,

Apurva

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Hi Apurva, got that, thank you!

Best Regards

xieyl

200311

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