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Nor Flash

New Contributor

In one of our program we are using the cypress S29GL512S Flash device for memory storage.

In verification stage we are trying to simulate the model (File name : s29gl512s.vhd) with our RTL, But the model is not up and running and stuck in reset state.

Kindly help to resolve the issue.

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5 Replies
Moderator
Moderator

Hi,

Could you please provide more details about testing and observing this failure?

Can you attach the waveform showing this issue?

Thanks and Regards,

Sudheesh

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New Contributor

Below is the screenshot. i have instantiated 5 flash models, none of them is responding. and below is the reset steps following it in testcase before start of the test.

initially in signal default, hreset_i <= '1';

            -----------------------------------

            wait for 310 us ; -- Before start of simulation wait for 300 us (Flash Model Power Up time)

            hreset_i <= '0';

            wait for 500 ns; -- wait for random time

            hreset_i <= '1';

1.PNG

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New Contributor

Please consider the below image, the above (1st) one is modified model code simulation.

And the 2nd one is no modification in the model. It ran as it is with rtl.

1.PNG

thanks sudeesh !

regards

sandeep

+91-8861288288

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New Contributor

Hi Sudheesh,

Please reply for the above post.

thank you !

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Moderator
Moderator

Hi,

We need additional details to help you with this issue.

1. How is the system connected? Which commands doesn't work exactly?

2. Are you using SDF or not?


Thanks and Regards,

Sudheesh

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