S25FS512 verilog model

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thanc_4239586
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I've found a SPI NOR Cypress S25fs512s Verilog Model (https://www.cypress.com/verilog/s25fs512s-verilog ) and I get confuse: Spec says that

   Read only bits are never modified and the related bits in the WRAR command data byte are ignored without setting a program or erase error indication (P_ERR or E_ERR in SR1V). Hence, the value of these bits in the WRAR data byte do not matter.

However in the model, I see that:

pastedImage_4.png    

SR1_V[7] is SRWD bit, it is a Volatile copy of SRWD_NV and a Read only bit, but in above code, it is always updated with data programed by WRAR command. If there is a mistake here ?

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Hello

Attached is the updated verilog model. pw is sse.

Thank you

Regards,

Bushra

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BushraH_91
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750 replies posted 50 likes received 250 solutions authored

Hello

Thank you for contacting Cypress Community Support. We have received your inquiry and currently reviewing the case. We will get back to you as soon as we find the resolution.

Have a wonderful day

Regards,

Bushra

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lock attach
Attachments are accessible only for community members.

Hello

Attached is the updated verilog model. pw is sse.

Thank you

Regards,

Bushra

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