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We have a PicoZed board with the S25FS128S QSPI that uses Xilinx FSBL, u-boot, etc. and everything worked perfectly until we had some event that cause the OTP bits in the configuration register to be set. By default, the FSBL uses the Zynq QSPI controller interface to read from the S25FS128S. However, the S25FS128S is in some sort of state that causes the linear read (memcpy from mapped addressed) from the QSPI to skip the first 32-bit word and thus fail to boot. I modified the FSBL to use the S25FS128S Quad Read command directly and that works fine (does not skip the first word). Any idea what state the S25FS128S chip is in that would cause the Zynq QSPI controller to not function correctly?
A power loss during a register write operation is a plausible explanation to the phenomenon you're observing. This can cause corruption to the status and configuration registers, and could even lead to OTP bits being set in these registers.
The reason for this is that these registers are also stored in a NV memory area and this area needs to be erased and reprogrammed in some cases.