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Nor Flash

Contributor II

Is there a time limit such as a timeout if there is a temporary waiting time during transmission / reception? If so, what would it behave? I couldn't find it in the datasheet.

In another device, there was a case where the SCL and SDA stuck at Low for a certain period of time (about 100ms) due to the SW processing of the master during I2C communication, and as a result, the slave device unintentionally timed out and the slave device reset. When I checked the specifications of the chip, the time-out specifications were listed, but it was not made with due consideration for SW.

I would like to check the specifications of the device to see if other devices are also considered.

 

Thanks,

Tetsuo

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Moderator
Moderator

Hello,

Our device S25FL512S uses SPI protocol (not I2C) and it won't get reset if there is a delay from master. But, it may ignore the command, if the instructions form master are not received properly. 

Could you please provide more details about the delay happening at master side? In SPI devices, each operation happens within a CS# cycle. See the program operation sequence as an example below,

Program sequence:

  1. CS# LOW
  2. WREN Command 
  3. CS# HIGH
  4. CS# LOW
  5. Send Program command
  6. Send Program address
  7. Send Program data
  8. CS#HIGH
  9. CS# LOW
  10. Read status register and check if the program operation is finished.
  11. CS# HIGH
  12. Repeat steps 9-11 until the program operation is finished. 

If the delay is in between the CS# cycles, then there won't be any issue. But, flash device may ignore the command, if it did not receive the instructions from master properly because of delay during a CS# cycle. You can find a related knowledge base article at: SPI clock frequency for Cypress SPI NOR flash devi... - Cypress Developer Community.

Please feel free to ask if you have any related queries.

Thanks and Regards,

Sudheesh

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1 Reply
Moderator
Moderator

Hello,

Our device S25FL512S uses SPI protocol (not I2C) and it won't get reset if there is a delay from master. But, it may ignore the command, if the instructions form master are not received properly. 

Could you please provide more details about the delay happening at master side? In SPI devices, each operation happens within a CS# cycle. See the program operation sequence as an example below,

Program sequence:

  1. CS# LOW
  2. WREN Command 
  3. CS# HIGH
  4. CS# LOW
  5. Send Program command
  6. Send Program address
  7. Send Program data
  8. CS#HIGH
  9. CS# LOW
  10. Read status register and check if the program operation is finished.
  11. CS# HIGH
  12. Repeat steps 9-11 until the program operation is finished. 

If the delay is in between the CS# cycles, then there won't be any issue. But, flash device may ignore the command, if it did not receive the instructions from master properly because of delay during a CS# cycle. You can find a related knowledge base article at: SPI clock frequency for Cypress SPI NOR flash devi... - Cypress Developer Community.

Please feel free to ask if you have any related queries.

Thanks and Regards,

Sudheesh

View solution in original post

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