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Hi, I am struggling to show that the timing analysis for the S25FL256S SPI Flash memory holds for Figure 5.10 SPI Single Bit Output Timing of the Document Number: 001-98283 Rev. *J.
The issue is that the Clock Low to Output Valid (tV) parameter max time delay is 8 ns, which violates the read operation setup time for AM3358 processor running in master mode with 48MHz clock frequency and 45/55 clock duty cycle. The AM3358 processor' Setup time(tsu(SOMI-SPICLKH)) (SOMI) valid before SPI_CLK active edge is 3.02 ns. Setup time margin = half period x duty cycle - tV - tsu = 9.36 - 8 - 3.02 = -1.66ns. However this example is application specific and out of your control, but I wanted to add the calculations for clarification.
Now assuming that one would like to run the SPI memory at say 100 MHz = 10 ns period = 5 ns half period, then given the Clock Low to Output Valid (tV) parameter max time delay of 8 ns and ignoring the delays related to clock duty cycle and master setup delays this should theoretically not work.
Please advise what am I missing..
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Hi Georgi,
As you stated tV parameter is 8 ns but please note it is a max spec. It may take less than that time also at ambient temperatures as you are seeing in the testing. At max temperature testing it may take 8 ns leaving 1.36 ns setup time for the master device which can result in a faulty read. Your understanding here is correct. In this case you have to reduce your operating frequency to include sufficient time for the processor.
Thanks,
Pradipta.