I found that it's a FPGA problem,I didn't use it right.
R23 pin is a configration pin,which should be tied to Vcc14 through a resistor,while I left it fload.
So the flash could do its job when I didn't use bank 14,when I use bank 14,it failed.
Hi,
Thank you for contacting Cypress Semiconductor.
Could you please tell me whether the FPGA is using Single SPI or Quad SPI to read the flash? If Quad SPI is being used, can you please check whether Quad mode has been enabled on the flash?
Regards,
Apurva
It's SPIX1 mode---single SPI mode.
Hi,
Thank you so much for the clarification.
Could you please tell me the reason for keeping pin 1 (HOLD# signal) LOW? If you go to page 10 of the datasheet you will find the explanation of the HOLD# signal. Driving the HOLD# signal LOW pauses any serial communication with the device.
Regards,
Apurva
I found that it's a FPGA problem,I didn't use it right.
R23 pin is a configration pin,which should be tied to Vcc14 through a resistor,while I left it fload.
So the flash could do its job when I didn't use bank 14,when I use bank 14,it failed.