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Nor Flash

SudheeshK
Moderator
Moderator

Hi,

During a read operation, you have to meet all of the three timing specs below to read data correctly from our flash device.

Address to Output Delay (tACC😞 Flash will drive data out within tACC time, if CE and OE signals are already active.

Chip Enable to Output Delay (tCE😞 Flash will drive data out within tCE time, if address is already stable and OE is active.

Output Enable to Output Delay (tOE😞 Flash will drive data out within tOE time, if address is already stable and CE is active.

In the waveform that you attached, OE signal is not active (LOW) when the address changes (marker 1). So, flash will not drive data out. When OE becomes LOW, it drives data out after tOE time. You are observing a longer delay from address change to output data is because of the delay for OE signal to become LOW after the address change, it is close to 1.3us.

To improve read time, you can change address and make OE signal LOW at the same time keeping CE LOW for the entire duration of read operation. Or, you can keep both OE and CE signals LOW for entire duration of read operation and change only address to read new data.

I hope the above information answers your query. Please feel free to ask if you need any clarifications.

Thanks and Regards,

Sudheesh

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KaFe_4587121
New Contributor

Hi Sudheesh,

I have another question regarding the AC timing.

I measured tGHQZ at 300+ ns. According to specs, max  should be 16ns. It also noted this spec is not 100% tested.

Any test conditions need to meet like tAAC, tCE, & tOE?

Thanks in advance.

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