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Nor Flash

New Contributor

Hi,

     We have interfaced "S29GL256P11FFIV20" Parallel NOR Flash with Xilinx Virtex 5 FPGA, We have 24 address lines and 16 data lines connected with FPGA. We have a softcore processor "PPC" module in FPGA which is being used to communicate with the device. We are using the drivers given by Cypress to read Device ID of the flash, but we are unable to read the correct data from the device. The operations which we have performed to read the device id are as follows

                  1.) FLASH WRITE :  BaseAddr + 0x0555 -> 0xAA (Unlock Cycle 1)

                  2.) FLASH WRITE :  BaseAddr + 0x02AA -> 0x55 (Unlock Cycle 2)

                  3.) FLASH WRITE :  BaseAddr + 0x0555 -> 0x90 (Write Autoselect command)

                  4.) FLASH READ :   BaseAddr + 0x01 Result : 0x90009000 (In correct)

  • Even the Manufacturer ID is being read in-correctly.
  • We have pulled Byte# pin to high and using word address commands.
  • We are using EMC IP in ISE to connect FLASH and PPC.
  • This IP is 32 bit addressing. In Verilog code, we are converting the 32-bit address to 24 bit and passing to flash.
  • Finally, our idea is to prove the interface by writing and reading the sectors/memory of the device.
  • We have a single Flash chip.

Attachments :

  • Flash and FPGA design schematics.
  • EMC IP timing Parameters.

Please have look at attachments and help us to resolve the issue.

Thanks & Regards,

Shaik Salauddin.

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Moderator
Moderator

Hello,

This issue can be because of wrong timing parameters. Could you please give a description for all the timing parameters shown in the image "emc_timing_parameters.png"? So that, we can compare them with the timing specs of our device. Timing parameters for our device is available on page 52 of the datasheet (https://www.cypress.com/file/219926/download ).

Also, please make sure that you are meeting the power up sequence timings given on page 55 of the datasheet.

What is the function of the flash device in your application? Are you using it to store FPGA configuration?

Thanks and Regards,

Sudheesh

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New Contributor

Hello Sudheeshk,

        Thanks for the quick response, Below I have described the timing parameters with respect to emc_timing_parameters.png image

Chip Enable to Data Valid (TCEDV)              0 ps
Address Valid to Data Valid (TAVDV)             0 ps
Chip Enable Disable to Data Bus High (THZCE) 1000 ps
Output Enable Disable to Data Bus High (THZOE)1000 ps
Write Cycle time (TWC)                     150000 ps
Minimum Write Enable Pulse Period (TWP)     50000 ps
Write Enable Disable to Databus low (TLZWE)    0 ps
Page access time for page mode flash (TPACC) 1000 ps

As suggested we will follow the power sequence and we will update you on that. The function of the flash in our application is to store the FPGA bootable image and also to store some data.

Thanks & Regards,

Shaik Salauddin.

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Moderator
Moderator

Hello,

I compared the timings parameters that you provided with the timing parameters of the flash. See table below.

    

FPGATiming specFlashTiming Spec
Chip Enable to Data Valid (TCEDV) 0 psChip Enable to Output Delay(tCE)110ns
Address Valid to Data Valid (TAVDV) 0 psAddress to Output Delay (tACC)110ns
Chip Enable Disable to Data Bus High (THZCE)        1000 psChip Enable to Output High Z (tDF)20ns
Output Enable Disable to Data Bus High (THZOE)        1000 psOutput Enable to Output High Z (tDF)20ns
Write Cycle time (TWC) 150000 psWrite Cycle Time (tWC)110ns
Minimum Write Enable Pulse Period (TWP) 50000 psWrite Pulse Width (tWP)35ns
Write Enable Disable to Databus low (TLZWE) 0 psData Hold Time (tDH)0ns
Page access time for page mode flash (TPACC)        1000 psPage Access Time (tPACC)25ns

As you can see, there are some differences between the timing specs. Could you please update the timing parameters as per the table above and test again? Also, make sure that you are following all the other timing specs given in datasheet of our flash device.

Thanks and Regards,

Sudheesh                                                                    

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