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Nor Flash

New Contributor II

Hi

At the datasheet of S25FL128SAGNFI000, Part 9.3.7 Write Registers (WRR 01h),it says

"After the Write Enable (WREN) command has been decoded successfully, the device will set the Write Enable Latch (WEL) in the

Status Register to enable any write operations."

When WREN 06h was sent to the flash chip, and the CS goes high, then the WEL should be set enable.

There is the question, how long it takes between the CS goes high and the WEL gets enable?

Sorry to ask that , i can't find it in the datasheet...

Thanks ...

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Moderator
Moderator

Hi,

The minimum CS# high time between two different operations in our device S25FL128S is "tCS". So, WEL bit will be set within tCS time from  CS# going HIGH after WREN command.

tCS (min) = 10ns (Read Instructions)

tCS (min) = 50ns (Program/Erase)

Thanks and Regards,

Sudheesh

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1 Reply
Moderator
Moderator

Hi,

The minimum CS# high time between two different operations in our device S25FL128S is "tCS". So, WEL bit will be set within tCS time from  CS# going HIGH after WREN command.

tCS (min) = 10ns (Read Instructions)

tCS (min) = 50ns (Program/Erase)

Thanks and Regards,

Sudheesh

View solution in original post

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