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Nor Flash

New Contributor II

Hi,

I am using the flash chip of CYPRESS, S25FL128SAGMFI000,  but I have some questions that I don't understand .

After power up, I did the RDSR1 command to read  the value of the Status Register 1 , I thought the SR1 value should be "00"H, but the result was "81"H.

(I did nothing after the chip was powered up, only read the SR1, besides, the RESET# was not used and was unconnected)

Could you help with to figure out why this happened?

here is the picture of the question.

0129.PNG

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Moderator
Moderator

Hi,

Sorry for the delay. As you mentioned, you have to meet all the timing requirements of our device to use it properly. You have to configure the FPGA to read data based on the signal delays on your PCB.

Thanks and Regards,

Sudheesh

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5 Replies
Moderator
Moderator

Hi,

As you mentioned, the default value of SR1 is 0x00. Could you please provide below details about this issue?

  • Did you do any operations to the flash device before reading status register value? Or, are you testing with a fresh device?
  • How many devices are showing this behavior? Are you observing it with all of the devices that you tested?
  • In the waveform that you attached, I did not see the signal "inst_FLASH_TOP/SO_bug" is always 1. Could you please explain how are you reading 0x81 from status register?
  • Please make sure that you follow power up timings given in datasheet. (Table 6 on page 25, https://www.cypress.com/file/448601/download )

Thanks and Regards,

Sudheesh

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New Contributor II

Hi,

Thank you so much for your reply!

Here are the answers to your questions:

1, Did you do any operations to the flash device before reading status register value? Or, are you testing with a fresh device?

---->The device is a new circuit board with the flash chip.

At first I didn't think there is the problem, so I did the WREN and WRR command to set the CR1, but when I wrote the WREN command and RDSR1 command to confirm the WEL is enable, I found the value of SR1 was not correct, and the WRR command hadn't been sent to the flash.

Then I read the SR1 at the beginning of the operation, I found the phenomenon as the picture.

2, How many devices are showing this behavior? Are you observing it with all of the devices that you tested?

----> Because  it is the development and test phase now, so I only have one equipment. The others will be sent here at the end of February.

3, In the waveform that you attached, I did not see the signal "inst_FLASH_TOP/SO_bug" is always 1. Could you please explain how are you reading 0x81 from status register?

----> I am using the FPGA to control the flash chip. And it is a question I am solving about debugging the SO signal.

Now, at my design, the command was sent with the SCK signal, and according to the sequence of command, the SO data will be sent out with the SCK, and the SO will be stored in the signal_vector of "RDSR1_i_08_00", and with the CS disable, the eight SR1 value will be stored in RDSR1_i_08_00 correctly.

4, Please make sure that you follow power up timings given in datasheet. (Table 6 on page 25,

----> After power up, there are dozens of seconds before I read the SR1. So I think the power-up timing is OK.

I will do some more test about this question.

And Please help me about this question.

Thank you very much !

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New Contributor II

Hi,

I did some more tests today. And I think I found why there errors happened. And can you please help me to confirm if the reasons are correct?

At the current project, the system is 200MCLK, and the flash module in the FPGA generates the SCK of FLASH chip with the 200MCLK.

Such as the RDSR1 function, the module generates SCK(100MCLK), but the delay in FPGA is about 6ns for the SO signal.

So when reading the SO after sending the RDSR1 command, the tcs time(5.4.2  Input / Output Timing of the datasheet) plus the delay in FPGA, I think the timing of this design can't reach the requirements of the chip datasheet.

So in today's test, I changed the 200MCLK(system clk) and 100MCLK (SCK) into 100MCLK(system clk) and 50MCLK (SCK), and the value of SR1 is correct, and I did the WRR command , and read back the SR1 and CR, the value is correct ,too.

So, I think the main reason of this error is that  the timing delay of my design can't reach the requirement of the chip.

But in fact, I must use the  200MCLK(system clk) and 100MCLK (SCK) in my design.( the 50MCLK (SCK) can't reach the read speed of my requirement even in QOR command)

So I think the best way to solve this problem is set the delay in FPGA and make the delay small as much as possible.

(but no matter how to set the delay, there much be a delay, maybe 1-2ns, maybe 2-3ns,etc. It depends on the whole project.)

So here is the question:

With your rich experience, is there some better way to solve this problem?

Or is there some better way for me to use for reference?

Thank you very much! and looking foward to your reply~~~

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Moderator
Moderator

Hi,

Sorry for the delay. As you mentioned, you have to meet all the timing requirements of our device to use it properly. You have to configure the FPGA to read data based on the signal delays on your PCB.

Thanks and Regards,

Sudheesh

View solution in original post

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New Contributor II

Hi,

Thank you so much for your reply!

I think I understand the question and I know how to fix it !

Thank you again and you relly help me a lot!

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