For S25FL128S, some questions about SDR AC Characteristics

xiaowei_li_3787 · ‎Mar 07, 2019

Hi,

I am using the flash chip of CYPRESS,S25FL128SAGNFI000, but I have some questions that I don't understand about the SDR AC Characteristics.

There is a question that I do not understand most.

At the datasheet of the chip, the 5.4 SDR AC Characteristics says that ( tV Clock Low to Output Valid can be 7.65 ns max ).(my stuation is note3 : 7.65 ns)

Here is the question, what is the most important influence factor to the time of tV?

In other words, when can the tV be the max value of 7.65 ns ? and when can the tV be the less value than 7.65 ns?

(In my design, the value of tV affect the reading timing sequence, so I want to make sure the tV can be controlled, otherwise my design will be influenced...)

So, wouly you help me to figure out this question?

Thank you very much!!!

SudheeshK · ‎Mar 21, 2019

Hi,

Please find more details about tV timing spec below.

Please refer the above diagram to understand about how tV parameter is defined from the flash point of view. Flash device will give data out during a read operation tV time after clock falling edge and it will be available on the SPI bus tHO time after the next clock falling edge. Data valid window to sample the data correctly by MCU will be as below.

Data valid window = Clock period (tPSCK) – tV(max) +tHO

Based on the available data valid window, MCU should decide when to sample the data while reading from flash. So, the maximum frequency with which a read operation can be performed depend upon the available data valid window and data setup time and data hold time requirements of MCU.

Please see the example below.

Frequency of operation (fSCK) = 100 MHz
Clock period (tPSCK) = 10ns
tV (max) = 8ns
tHO (output hold time of flash device) = 2ns

Data valid window = tPSCK – tV + tHO = 10 – 8 + 2 = 4 ns.

Let us consider the setup time and hold time requirements of MCU as below.

Input setup time of MCU = 2 ns
Input hold time of MCU = 2 ns
Minimum data valid window required = 4ns

Then, it is possible to sample the data along with the falling edge of same SPI clock by MCU. See red line in the above diagram.

If the setup time and hold times of MCU are as below,

Input setup time of MCU = 5 ns
Input hold time of MCU = 2 ns
Minimum data valid window required = 7ns

Since the data valid window available is only 4 ns, MCU won’t be able to sample output data correctly in this case. SPI clock frequency should be reduced to make the data valid window wider, such that the setup time and hold time of MCU are met.

Users can take below actions to make the data valid window wide, if the setup time and hold time requirements of MCU are not met.

Reduce CL to reduce tV value.
Reduce SPI clock frequency.

In the 'bad' case that you mentioned, you may need to reduce the SPI clock frequency to sample output data from flash at the rising edge of the clock.

Thanks and Regards,

Sudheesh

View solution in original post

For S25FL128S, some questions about SDR AC Characteristics

For S25FL128S, some questions about SDR AC Characteristics

Re: For S25FL128S, some questions about SDR AC Characteristics