DDR operation of S28HS256T / S28HS512T / S28HS01GT flash

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LaSa_4608831
Level 1
Level 1

Hello,

We're working on a controller project targeted for S28HS256T / S28HS512T / S28HS01GT flash device.

When we set the flash model to OPI DDR, we noticed there's an extra DS pulse after every read.

Is this expected?

Attached is a screenshot of waveforms.

Thanks in advance.

Regards,

Lawrence

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1 Solution
SudheeshK
Moderator
Moderator
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250 sign-ins First question asked 750 replies posted

Hi Lawrence Salazar,

During a read operation, our device will drive data out as long as the master give clock signal. As mentioned in the datasheet "During the period of data transfer in read transactions, the DS signal is driven by the device and transitions with the DQ signal data transitions".  So, the DS signal will toggle as long as the master is reading data from the flash by providing clock signal. Once the clock signal from master stops, DS output from flash devices will also stops toggling.

In the waveform that you attached, there is a delay for CS# signal to go HIGH after SCK signal stops. The extra DS pulse that you mentioned happens during this time. So, it is expected and not an issue. Please feel free to ask, if you need any clarifications.

Are you facing any issue with read, program or erase operations?

Thanks and Regards,

Sudheesh

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4 Replies
SudheeshK
Moderator
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Moderator
250 sign-ins First question asked 750 replies posted

Hi Lawrence Salazar,

During a read operation, our device will drive data out as long as the master give clock signal. As mentioned in the datasheet "During the period of data transfer in read transactions, the DS signal is driven by the device and transitions with the DQ signal data transitions".  So, the DS signal will toggle as long as the master is reading data from the flash by providing clock signal. Once the clock signal from master stops, DS output from flash devices will also stops toggling.

In the waveform that you attached, there is a delay for CS# signal to go HIGH after SCK signal stops. The extra DS pulse that you mentioned happens during this time. So, it is expected and not an issue. Please feel free to ask, if you need any clarifications.

Are you facing any issue with read, program or erase operations?

Thanks and Regards,

Sudheesh

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Hello Sudheesh,

Thanks for the quick response.

Yes we are having issue with using the flash in OPI DDR mode due to the extra DS cycle.

The latency provided is according to the datasheet and tested ok in OPI SDR mode.

I'd like to continue the discussion in "semper-flash" group so the details can be more specific.

Can you share how I could join this group?

Regards,

Lawrence

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Hi Lawrence Salazar,

Could you please provide more details about the issue that you have because of the extra pulse on DS signal?

Also, please let me know about the "Semper flash group" that you are referring to.

Thanks and Regards,

Sudheesh

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Hello Sudheesh,

Thanks for the response.

Our flash controller detects the extra pulse on DS signal when in OPI DDR mode as unexpected data input from flash.

Regarding the "Semper flash group", I was able to join via https://go.cypress.com/semper-access-program-ap

Will continue my inquiries on this group.

Thanks for the assistance.

Regards,

Lawrence

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