Cannot write data to S25FL256SAGNFI003

[qspace]

I tried to custom SQI Flash driver from the MpLAB Harmony framework but it does not work.

I can get the ID of the S25FL256SAGNFI003 using RDID cmd, but cannot write data to it using 4QPP cmd. 

After erase and write data to flash, I use DMA mode to read data from flash but all data return is 0x00.

I check the signal of the IO2 and IO3 line and notice the IDLE state of these lines are high level, IO0 and IO1 are low levels. Does it affect communication?

I attached the code and schematic here for reference.

[Apurva_S]

Hi @qspace 

You can take a look at our low level driver and try to match it with your driver to see if the sequence of commands is correct. You can download our driver from here - https://www.cypress.com/documentation/software-and-drivers/low-level-driver-spi-flash?source=search&...

In case you decide to use our LLD in your application, you can check the sample project attached in this thread to learn more about the implementation -https://community.cypress.com/t5/Nor-Flash/S25FL064L-64-Mb-8-MB-3-0-V-FL-L-SPI-Flash-Memor/m-p/26451...

In order to use 4QPP command for page program operation, you will have to enable Quad mode on both flash and controller side. For enabling Quad mode on flash side, you need to set the QUAD bit (CR1[1]) in Configuration Register 1. Hope you have enabled Quad mode on the controller side as well. Also, 4QPP command expects 4 byte address after the command. The sequence of commands would be like - 

• Drive CS# LOW
• Send WREN command
• Drive CS# HIGH
• Drive CS# LOW
• Send WRR command
• Send SR1 value
• Send CR1 value (QUAD bit set)
• Drive CS# HIGH
• Drive CS# LOW
• Read SR1
• Drive CS# HIGH
• Check the value of WIP and error bits. Keep checking the value of SR1 till WIP bit goes LOW. If the program error bit is set, it indicates that the program operation was not successful. In this case, you will have to clear the error bits from the SR and retry. If the WIP bit goes LOW and none of the error bits are set, it indicates successful completion. You can read the CR to verify the value.
• Drive CS# LOW
• Send WREN command
• Drive CS# HIGH
• Drive CS# LOW
• Send 4QPP command
• Send 4 byte address
• Send data bytes
• Drive CS# HIGH
• Drive CS# LOW
• Read SR1
• Drive CS# HIGH
• Check the value of WIP and error bits. Keep checking the value of SR1 till WIP bit goes LOW. If the program error bit is set, it indicates that the program operation was not successful. In this case, you will have to clear the error bits from the SR and retry. If the WIP bit goes LOW and none of the error bits are set, it indicates successful completion. You can read the flash to verify the data.

I check the signal of the IO2 and IO3 line and notice the IDLE state of these lines are high level, IO0 and IO1 are low levels. Does it affect communication? Please see Table 3 on page 18 of the datasheet. In standby state, SO/IO1 line does not have a driver and is in floating state, whereas IO0, IO2, IO3 can either be driven by the host of remain floating. It will not affect the communication.

Is erase/program operation working in single SPI mode? Did you try to check?

I would like to request you to capture the spi waveforms and provide us screenshots.

Regards.