I would like to get errata information about CY15B104Q-LHXIT.
Are there any errata?
For better bus utilization on our system we use 32 bit width, including 32 bit spi transfer. It has the side effect that WEL opcode/command is sent as a 4 byte command which has worked fine in the past, using the FRAM device CY15B104Q. Now that we have changed to FRAM device CY15X108QI it does not work anymore. We have tried to have the WEL opcode first, last or fill all bytes, including having the other bytes as 0s, 1s or 55 which I think was mentioned as idle pattern, nothing makes the WEL latch when using 32 bit transfer. Sending the WEL opcode as a single byte works as expected, but is not how we would preferably do this.
The attached data is captured for the two devices using digital analyzer, and show
CY15B104Q accepting 32 bit transfer for WEL:
CY15B104Q_working
CY15X108QI not accepting 32 bit transfer for WEL:CY15X108QI _not_working
Is it, should it be possible? It worked in the past for other chip? Please advice.
Show Less我們使用FM24CL64B-GTR于产品应用。
因为之前是有看到富士通的FRAM的datasheet中是有关于ESD和闩锁方面的说明的,因此想了解下CYPRESS的FRAM是否也有这方面的说明,只是未在datasheet中展示,另外FRAM芯片设计中是否又对闩锁问题在半导体层面做加强处理或工艺加强?
如果FRAM因為ESD發生閂鎖,那對存儲在裡面的資料會有什麼影響?
閂鎖後輕的結果或者嚴重的後果會是什麼?
Show LessDear Cypress-Community,
we use the FRAM FM28V020-SG since over 10 years, and we had no problems for a long time. In this fine working time period we use FM28V020-SG with second number e.g. "A 1601602287" or older...
But since end of 2018 the FM28V020-SG with second number G 1749647029 makes more and more problems.
Since April 2020 5% of our boards with FM28V020 lost some bytes (we are always testing the F-RAM Memory each 2seconds --> we get checksum errors since FM28V020-SG with seconde number G 1749647029).
Can you say me, what has changed from older to newer FM28V020-SG Versions ?
Does something was changed in the Maximum Ratings? Or was there a change in the operating range?
Or was there a change in the timing? Or anything else?
Thanks a lot for your answer(s).
Best regards
Markus T. from Germany
Show LessDear Support team,
FRAM FM25V10 datasheet mentions that the device specifications are guaranteed over an industrial temperature range of –40°C to +85°C. But under maximum ratings section Ambient temperature range with power applied is mentioned to be –55°C to +125°C. I was wondering whether it is possible to operate this FRAM above 85°C upto 125°C? Will it behave in the same manner as specified in the datasheet, in this case?
Thanking you in advance.
Show LessHello,
I am using the Verilog Simulation Model of the FM24V10 (FM24V10 - VERILOG.zip (cypress.com)) and encountered the following problem: TheSimulation model seems to have a write buffer of 128 bytes, see line 80 of file FRAM_I2C.v:
reg [07:00] WrDataByte [0:127]; // memory write data buffer
Hence, sending datagrams of length > 128 Bytes result in data loss. However, I can not find any information regarding a size limitation of writes in the datasheet (FM24V10, 1-Mbit (128K × 😎 Serial (I2C) F-RAM (cypress.com)).
Can anyone confirm that there is mismatch between datasheet and model? Does the device have a writebuffer of size 128 byte?
Thank you. Best regards
Jan
Show Less
Datasheet says "2.6 mA (typ) active current at 40 MHz." Does the current scale with frequency? What would be the current for 8bit data at 1kHz?
Also, would FRAM be MRI safe?
Show LessAre there any shock and vibration test data for the F-ram product line?
I want to use several 8Mbit x8 SPI 40MHz Excelon LP F-RAM devices in an application where I need to convert signals coming from a parallel x8 SRAM interface to 40MHz SPI signals and also 40MHz SPI signals sourced from the SPI F-RAM device to signals destined for the x8 parallel SRAM interface. As for the x8 parallel SRAM interface timings, conservatively, I have a memory address setup time of around 250ns, a memory address hold time of around 1250ns and a chip enable hold time of around 750ns ( I'm not quite sure of the timings right now and I know I am missing some timing information for some of the x8 parallel SRAM signals ). I plan on doing this with an ultra-low-power MCU, but, I'd need to use cycle-stretching on the Cypress F-RAM device(s). Is the above kind of conversion doable, especially the cycle stretching?
( N.B. The devices I want to use are one of these : https://www.cypress.com/file/444186/download , https://www.cypress.com/file/444186/download )
Thanks,
jdb2
Show LessHello Community,
Greetings for the day!
Myself Vipul Prajapati working as Sr. Engineer at Eaton India Innovation Center, Pune, India for the Power system division group. This is with reference to get the details of standard bitbang SPI routine sample code to do word write into cypress FRAM - CY15E016Q.
We are currently working for a project which uses NXP Legacy automotive MCU (PN - M68HC16Z1). To support the ongoing firmware development, we would require to write SPI bitbang routine in existing FW which can write word by word data to FRAM chip. As this project is with legacy development, running from last 18 years with very limited MCU support, It would be difficult for us to write SPI routine which can do the job without affecting the existing FW.
Could you please help us to provide the sample SPI routine which can be utilize to write word by word data to FRAM chip CY15E016Q? Thanks in advance!
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