Non Volatile RAM (F-RAM & NVSRAM) Forum Discussions
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Regarding the FRAM reset method, it seems that there are two methods, hardware reset / software reset, but please give us information on each reset condition.
MPN: FM24V02A-GTR
Show Less1. With respect to the NVSRAM (CY14B256LA-SP25XIT) what it the structure/impedance between the power pin(s), VCC, and the storage cap Vcap.
2. If given a step change in VCC during power on, 0 – 3.3V, what limits the current through the chip to the storage capacitor? Would that maximum current or impedance be the same for a ramped VCC, e.g. a soft-start?
3. The data sheet would suggest that the hardware auto-recall (See Note 25. on page 13 of the datasheet) is only a function of the voltage on the VCC and not the Vcap pin voltage, is this correct?
4. In the CY14B256LA data sheet under maximum device ratings on page 8 there is a maximum accumulated storage time:
Maximum accumulated storage time:
At 150 C ambient temperature .......................1000 h
At 85 C ambient temperature ..................... 20 years
- Are these limitations against the storage of data or with respect to the useful life of the component?
- Does the storage temperature / time impart physical changes, damage, to the component or is it just with respect to the data storage?
- Are there any internal manufacturing structures, e.g. flash, which are used to mask defective structures, array elements, to increase the yield of the device which would be adversely affected by the storage temperature?
- If just with respect to the storage of data, would rewriting the array reset the 1000h accumulated storage time?
- Can the storage temperature to data integrity, or component life, be defined? E.g. above 85C device data integrity, or life, decreases exponentially or perhaps linearly with respect to accumulated time at temperature?
5. What are the architectural differences between the that drive the change in the auto-recall and software recall times as compared to the STK14C88? Reference Infineon app-note AN55662_Migrating_from_STK14C88-3_to_CY14B256LA-ApplicationNotes-v06_00-EN. I’m not looking for too deep of an answer, really zoomed out or high level features would be sufficient, like the internal controller/state machine includes enhanced error detection and correction, clearing or setting of dirty data dirty bits, indicative of a un-saved write operations, slower non-volatile memory…
6. Since the components are screened for temperature, is there an estimate for the time each component was powered during testing at elevated temperatures? I’m assuming that it was fairly minimal, a few seconds too perhaps a couple of minutes each. I guess a valid conservative estimate would be the total test time at temperature divided by the number of components tested?
Show LessHi,
We will support to design in CY14B101LA-SZ45XIT NVRAM.
Have we NVRAM layout guideline to conform it?
Ex:Impedance, line width/line interval space/line length information
Regard,
Kevin
Show LessI see other posts asking if the CY14E256LA-SZ25XI was obsolete and Infineon states full production. Digi-key and Mouser list as Obsolete. Digi-key sent me the attached list (PD220902A) of Product Discontinuation. It lists the CY14E256LA-SZ25XI as being obsolete with the 3.3V chip (CY14B256LA-SP25XI) as the Next Best Alternative Part.
Is this list of discontinued Memory Products correct?
How was this list generated if the part had not been Discontinued.
Should I make a case to redesign all our assemblies or are these parts not be in Discontinued?
Thanks
-Aaron
Show LessHi,
Soft Error Rate discussion on NvRAM in thread from 10/16/2018 06:00PM provided a Report file to the discussion initiator. Are similar SEU/SEL report files available on NvRAM parts STK14C88-3NF35I and CY14B256LA-SZ25XIT?
Thank You,
Jim
Show Less- CY15B004Q does not have unique SN features, neither the OP commands regarding to this functionality.
- CY15B004Q does not allow fast reads or writes.
- CY15B004Q has only 4Kbit (512 * 😎 instead of 1Mbit (128k * 8).
- CY15B004Q has a logic bug in the state machine, where the OP code byte 0x0A does not trigger clearing the WEL bit.
- CY15B004Q has 0 - 16 Mhz speed instead of FM25V10 0-40Mhz.
In the Write operation, if / WE is asserted and then negated earlier than the Min value of tpwe,
Is the content of SRAM at the address undefined? Or does the previous value remain?
If it is undefined, if the power is turned off and then turned on in that state, the SRAM → nvSRAM store operation (@power off) will be performed as an indefinite value.
Does nvSRAM → SRAM recall operation (@ power ON) and nvSRAM operates with an undefined value?
Show Lesswe have a prototyping board equipped with fram (part number cy15v108qn-20lpxi). The mcu controller is ti's cc2640r2f. I have tried both gpio bitbang and spi hardware to read status register. The results are the same. the first byte, 0x05, is issued from mcu and the fram chip did respond a byte, an 0x0c, which is an illegal value according to manual, since the bit 6 is not set. Also bit 2 & bit 3 is not the default value (supposed to be 0).
Attached are waveforms I photoed from my osilloscope (sorry that i have only a low-cost, dual-channel one at hand, but I think it is enough for the job). One shows the first byte is 0x05, correctly issued from the host. The other shows the second byte replied from fram. The wave form looks OK but the value 0x0c is incorrect according to datasheet.
Also, I have tried to read device id (0x9f) and unique id (0x4c). Both commands returned only zeros, which seems to be incorrect.
any good explanations for the problems? or any timing error in wave forms? or the chips are broken? shed me some light.
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I am trying to read the Device ID from a CY15B104QN-50SXA chip and am getting out 0x402CC27F7F7F7F7F7F, which is the LSB to MSB read of the actual device ID listed in the datasheet, 0x7F7F7F7F7F7FC22C40. The datasheet claims the chip should read it out MSB to LSB, is there a reason this wouldn't be the case? Are other read/write operations affected as well?
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