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Yes, I know there's a Verilog model. We are a VHDL house, so we need a VHDL model for this device. Cypress, can you help out?
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Hi Andy,
Since both are HDLs a model in either one of the languages serves the purpose of having a simulation model.
Thanks,
Pradipta.
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Whil
PradiptaB_11 wrote:
Since both are HDLs a model in either one of the languages serves the purpose of having a simulation model.
Thanks,
Pradipta.
That is true, but beside the point.
As I noted in the original post, we are a VHDL house. To use a Verilog model in an otherwise VHDL design requires a mixed-language simulator, and both Aldec and ModelSim charge a lot of money (easily in the five figures) for such tools. That expense makes no sense when the only need for mixed-language simulation is to deal with an occasional Verilog model.
That said, I could write a VHDL model of this memory device. But the point of using a vendor-supplied model is that you know all of the details of the device and we can presume that your model is golden. My model is my best guess as to how your part really works. I can't verify my FPGA design using my guesses as to how your part works.
I hope why we need a VHDL model is clear.