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Non Volatile RAM (F-RAM & NVSRAM)

jdb2
New Contributor II

I want to use several 8Mbit x8 SPI 40MHz Excelon LP F-RAM devices in an application where I need to convert signals coming from a parallel x8 SRAM interface to 40MHz SPI signals and also 40MHz SPI signals sourced from the SPI F-RAM device to signals destined for the x8 parallel SRAM interface. As for the x8 parallel SRAM interface timings, conservatively, I have a memory address setup time of around 250ns, a memory address hold time of around 1250ns and a chip enable hold time of around 750ns ( I'm not quite sure of the timings right now and I know I am missing some timing information for some of the x8 parallel SRAM signals ). I plan on doing this with an ultra-low-power MCU, but, I'd need to use cycle-stretching on the Cypress F-RAM device(s). Is the above kind of conversion doable, especially the cycle stretching?

( N.B. The devices I want to use are one of these : https://www.cypress.com/file/444186/download , https://www.cypress.com/file/444186/download )

Thanks,

jdb2

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SudheeshK
Moderator
Moderator

Hello,

Yes,  you are correct.  You have to send a WREN command before a write operation. The correct sequence will be as below.

Write

  1. Select FRAM device. CS# LOW
  2. Send WREN command
  3. Deselect FRAM device. CS# HIGH
  4. Select FRAM device. CS# LOW
  5. Send Write command to FRAM
  6. Send Write address to FRAM
  7. Convert data from parallel to serial interface. SPI clock stays idle during this time. FRAM is still selected.
  8. Send data to FRAM
  9. Repeat steps 4-5 until all the bytes are sent to FRAM.
  10. After sending data, FRAM is deselected CS# HIGH

 

As mentioned in the datasheet, the maximum SPI clock speed supported by our device is 40MHz. We cannot guarantee any of the datasheet parameters, if operated at a frequency greater than 40Mz.

Please check our devices below, they can support SPI clock frequency up to 108MHz.

  1. https://www.cypress.com/file/497061/download
  2. https://www.cypress.com/file/400726/download 

Thanks and Regards,

Sudheesh

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SudheeshK
Moderator
Moderator

Hello,

 

Sorry for the delay in our response. Please find our comments about your query below.

 

I assume that by "Clock stretching" you mean that SPI clock signal to our FRAM will become idle after transferring each byte and FRAM device will remain selected (CS# LOW). Please correct me if I am wrong.

 

There is no issue for our device, if SCK signal become idle during an SPI operation (read/write). Please see the description for SCK pin given in our datasheets, "All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge of the serial clock. The clock frequency may be any value between 0 and 40 MHz and may be interrupted at any time due to its synchronous behavior". As input and output are synchronized to rising and falling edge of the clock respectively, there won't be any issue if SCK signal stays idle for some time.

 

Please feel free to ask if you need any clarifications.

 

Thanks and Regards,

Sudheesh

jdb2
New Contributor II

I think my original question was a little unclear. To interface the Cypress F-RAM SPI device with a device that does reads and writes via an x8 parallel SRAM-like interface, I'll have an MCU or an FPGA / CPLD sampling the memory address, chip enable and read / write enable lines of the parallel interface. First, the SPI clock will usually be held idle. When the chip enable goes low ( it's active low ) and the read / write line indicates that a read is intended, my circuitry will issue the necessary SPI commands to initiate a read of the F-RAM, send the address to the F-RAM at 40MHz and then read the F-RAM via the SPI bus at 40MHz. During the read, my circuitry will cache 8-bits ( a byte ) of data in a shift register and then output it in parallel from said register to the x8 parallel SRAM-like interface device, then the SPI clock will go low and stay idle. When a write is indicated, the process is similar, except the commands to perform a write are first driven onto the SPI bus, then, the SPI lock goes idle while 8 bits of data are collected by another register ( in parallel ). Then, the SPI bus cycle is completed by shifting the 8 bits out of the aforementioned register and onto the SPI bus as the data to be written to the F-RAM.

Since the Cypress SPI F-RAM in question seems to only care about the edges of the clock, as long as the total clock period is greater or equal than 25ns ( which of course corresponds to 40MHz ), I think my method will work, especially with your helpful and informative comments -- I just need confirmation.

Thanks and regards,

jdb2

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SudheeshK
Moderator
Moderator

Hello,

 

Yes, as mentioned our datasheet input and output of our SPI FRAM is synchronized to the SPI clock edges. As long as the SPI clock frequency is less than 40MHz, you will be able to perform read and write operations to the FRAM. 

As per my understanding, the sequence of operations for read and write from FRAM are as below.

Read

  1. Select FRAM device. CS# LOW
  2. Send Read command to FRAM
  3. Send Read address to FRAM
  4. Read data from FRAM. 
    1. After reading each byte, it is converted to parallel interface and send to the parallel device. 
    2. During this time (conversion from serial to parallel) SPI clock stays idle and the FRAM is still selected.
  5. Repeat step 4 until reading the required number of bytes from FRAM.
  6. After read, FRAM is deselected CS# HIGH

Write

  1. Select FRAM device. CS# LOW
  2. Send Write command to FRAM
  3. Send Write address to FRAM
  4. Convert data from parallel to serial interface. SPI clock stays idle during this time. FRAM is still selected.
  5. Send data to FRAM
  6. Repeat steps 4-5 until all the bytes are sent to FRAM.
  7. After sending data, FRAM is deselected CS# HIGH

Please correct me if I am wrong. If you are implementing above sequence of operations with FRAM, then there won't be any issues.

 

Thanks and Regards,
Sudheesh

jdb2
New Contributor II

Thanks for the reply 🙂 What you outlined is basically what I intend to do. One thing you left out is that for a write operation to the F-RAM device, the WREN SPI bus command has to be issued first to set the internal write-enable latch before the WRITE command is issued.

The only problems I see with my approach is that, even at 40MHz, the 25ns SPI clock cycle period of the 40MHz F-RAM device may *still* be too slow even though I want to interface it with a device that has an 8-bit parallel SRAM-like interface that runs at only 4MHz. The reason is that the address and data setup times are around 250ns, but, the Cypress Semi F-RAM device would require 25ns*8 + 25ns*8 + 25ns*8*3 + 25ns*8 = 1200ns 😕 ( Unless I bungled the calculation ). I really don't see a way around this unless Cypress Semiconductor comes out with faster SPI F-RAM chips.

Regards,

jdb2

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jdb2
New Contributor II

Specifically, if the Cypress Semi F-RAM SPI clock speed was increased to at least 192MHz ( which is 4.8 times the current 40MHz speed ), then that would solve a lot of problems.

Regards,

jdb2

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SudheeshK
Moderator
Moderator

Hello,

Yes,  you are correct.  You have to send a WREN command before a write operation. The correct sequence will be as below.

Write

  1. Select FRAM device. CS# LOW
  2. Send WREN command
  3. Deselect FRAM device. CS# HIGH
  4. Select FRAM device. CS# LOW
  5. Send Write command to FRAM
  6. Send Write address to FRAM
  7. Convert data from parallel to serial interface. SPI clock stays idle during this time. FRAM is still selected.
  8. Send data to FRAM
  9. Repeat steps 4-5 until all the bytes are sent to FRAM.
  10. After sending data, FRAM is deselected CS# HIGH

 

As mentioned in the datasheet, the maximum SPI clock speed supported by our device is 40MHz. We cannot guarantee any of the datasheet parameters, if operated at a frequency greater than 40Mz.

Please check our devices below, they can support SPI clock frequency up to 108MHz.

  1. https://www.cypress.com/file/497061/download
  2. https://www.cypress.com/file/400726/download 

Thanks and Regards,

Sudheesh

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