We don't have any ready to share PCB layout design guidelines for specifically for the CY14B101P in SOIC 16 package option. We consider that CY14B101P is a standard SPI memory which operates at maximum 40 MHz SPI frequency. If the layout designer follows the defacto PCB layout standard practices, this will be sufficient to achieve good SI without any challenge. However this doesn't apply for the RTC circuitry as this requires special attention to get the best clock accuracy. We have published an application note (AN61546) http://www.cypress.com/?rID=45439 which discusses about RTC best design practices in details including PCB layout for all nvSRAMs including CY14B101P.
We don't have any ready to share PCB layout design guidelines for specifically for the CY14B101P in SOIC 16 package option. We consider that CY14B101P is a standard SPI memory which operates at maximum 40 MHz SPI frequency. If the layout designer follows the defacto PCB layout standard practices, this will be sufficient to achieve good SI without any challenge. However this doesn't apply for the RTC circuitry as this requires special attention to get the best clock accuracy. We have published an application note (AN61546) http://www.cypress.com/?rID=45439 which discusses about RTC best design practices in details including PCB layout for all nvSRAMs including CY14B101P.
