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Non Volatile RAM (F-RAM & NVSRAM)

zunda
New Contributor

Hi.

FM25C160B-GTR is under consideration.

We plan to write 16 bytes of recorded data (including CRC) on one line and the next recorded data alternately on another line.
Since there is no power failure detection circuit, writing by power failure detection is not performed.
If the data becomes CRC abnormal due to a power failure and writing, both lines are read after the power is restored and the CRC normal recording data is adopted.
Can it be used this way (without detecting a power outage)?
Also, for example, does a power outage and writing hit and both lines become abnormal data? ..

Thank you

Jun

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1 Solution
PradiptaB_11
Moderator
Moderator

Hi Zunda,

4.5 V is the minimum voltage that we can guarantee from our side. At this voltage level the FRAM will function or operate normally. Now below this say at 4.4 or 4.3 V the device may work or may not work but we cannot guarantee the device functionality below 4.5 V. 

If you notice any fluctuations in power which causes the VDD voltage to go below 4.5 V during a write or a read operation the byte that was last sent to the device (during write) or the byte that was last outputted by the device will be reliable. After that any data will not be reliable. For example say i gave a command to write to address 0 of the fram and i am providing 6 bytes of data to be written. So 1st byte will go to address 0 and 2nd will go to address loaction 0x0001 and so on. Now say there is a power fluctuation while writing the 4th byte to the device.   So the first 3 bytes that are written will reliable data but the next 3 bytes of data will not be reliable. So address location 0x0003 to 0x0005 will contain garbage values.

Thanks,

Pradipta.

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3 Replies
PradiptaB_11
Moderator
Moderator

Hi,

The F-RAM architecture is based on an array of rows and columns of 256 rows of 64-bits each. So each row can store 8 bytes of data. It is unclear to us as to what do mean by one line and how will you be storing 16 bytes of data on it. 

Also can you explain your mechanism in more details and maybe provide an example as well. Please note  If the power is lost in the middle of the write operation, only the last completed byte will be written. Internally there is a 8 bytes buffer inside the device and say for example you were able to communicate only 4 bytes via SPI before power outage then only 4 bytes will be holding valid data. The other 4 bytes will contain non reliable data.

Thanks,

Pradipta.

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zunda
New Contributor

Thank you for your reply.

It turns out that the last data has been written.
Does it mean that the last data timing is when the FRAM VDD drops below 4.5V?
Does that mean that when the FRAM's VDD drops below 4.5V, the FRAM will stop working?

# The operating voltage of the CPU is lower than 4.5V.

best regards.

zunda

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PradiptaB_11
Moderator
Moderator

Hi Zunda,

4.5 V is the minimum voltage that we can guarantee from our side. At this voltage level the FRAM will function or operate normally. Now below this say at 4.4 or 4.3 V the device may work or may not work but we cannot guarantee the device functionality below 4.5 V. 

If you notice any fluctuations in power which causes the VDD voltage to go below 4.5 V during a write or a read operation the byte that was last sent to the device (during write) or the byte that was last outputted by the device will be reliable. After that any data will not be reliable. For example say i gave a command to write to address 0 of the fram and i am providing 6 bytes of data to be written. So 1st byte will go to address 0 and 2nd will go to address loaction 0x0001 and so on. Now say there is a power fluctuation while writing the 4th byte to the device.   So the first 3 bytes that are written will reliable data but the next 3 bytes of data will not be reliable. So address location 0x0003 to 0x0005 will contain garbage values.

Thanks,

Pradipta.

View solution in original post

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