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Non Volatile RAM (F-RAM & NVSRAM)

Sailesh
New Contributor

Hello,

The downloaded document from https://www.cypress.com/file/444186/download,shows on Pg 17, it's endurance limit of 432 yrs, operating at SCK freq of 40Mhz. These calculations r based on reading 64 byte data sequentially.

If I do random Fast-Read continuously then based on the same calculations the endurance cycles/sec comes to 800,000 (this includes CS disable time of 50nSec) and the yrs to reach this limit falls to ~40

I want to know if I am on the right track or there's something more to it?

Thanks,

Regards,

Sailesh..

 

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1 Solution
PradiptaB_11
Moderator
Moderator

Hi Sailesh,

We have a KBA on Endurance limit calculation. I am adding the link below for reference. 

I am not able to follow your calculations for fast read opcode. Can you provide us more details on them for us to better understand them.

https://community.cypress.com/t5/Knowledge-Base-Articles/Calculation-of-Endurance-Limit-for-FRAM-Dev...

Thanks,

Pradipta.

View solution in original post

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3 Replies
PradiptaB_11
Moderator
Moderator

Hi Sailesh,

We have a KBA on Endurance limit calculation. I am adding the link below for reference. 

I am not able to follow your calculations for fast read opcode. Can you provide us more details on them for us to better understand them.

https://community.cypress.com/t5/Knowledge-Base-Articles/Calculation-of-Endurance-Limit-for-FRAM-Dev...

Thanks,

Pradipta.

View solution in original post

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Sailesh
New Contributor

Hello Pradipta,

let's presume I am reading randomly, I have Instruction(8b)+Address(24b)+Dummy(8b)+Data(8b) = 48bits. Operating SCK at 40 Mhz will mean 1.2uSec have elapsed. If I add 50nSec to terminate this and start another random address reading it'll mean I have repetition 1/1.25uSec or 800,000 cycles/sec.

The internal architecture will still access 64bytes, read and write back at 1.25uSec rate.

800,000 cycles/sec comes to 25.2 x10^12 cycles/year.  Hence to reach endurance of 1x10^15 it will take  39.64 years.

Hope I am clear about this and let me know if I am missing anything.

Thanks,

Regards,

Sailesh..

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PradiptaB_11
Moderator
Moderator

Hi Sailesh,

For completing a random read operation at 40 MHz you will take 1.2 uSec this is true. If we look into the internal fram architecture this fram device has 32K rows of 64 bits each (8 data bytes). So each row can hold 8 bytes and whether out of this 8 only 1 byte is accessed or all of them is accessed it will be considered as 1 endurance cycle for all the cells in the particular row. 

Now in your example after reading this particular row you are reading the same row again in the next 1.25 uSec and this cycle repeats which will give the endurance cycle to be 800000 per second as per your calculation. (If you would have read some other row as in our documented example then the endurance cycle for this row and the next row you read will now be 1 instead of only one row having 2 cycles after two reads. In the datasheet 64 bytes of data is written sequentially so 8 different rows will be written and then looped.) No practical application will continue to read the same location again and again and not even process the data it reads. (Processing will again add time in between reads thus increasing 1.25 uSec value) So if we take all this factors into considerations the lifetime of the fram will increase from your calculated 40 years. In practice you can be assured that the fram will outlast the application lifetime expectancy. 

Thanks,

Pradipta.  

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