SPI Rx FIFO size limitations in MTB API's

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BiM_4640481
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Hello,

I am trying to integrate Toshiba flash driver code with Bootloader(version 1.x) code of PSoC6-43012 in MTB. Earlier I had posted a query related to reading the device id of flash, and it got resolved in following thread, solved by @https://community.cypress.com/t5/PSoC-6-MCU/SCB-SPI-transmit-and-receive-buffer-size/td-p/277228

Continuing working with flash I need to read flash sectors or pages  using PDL API Cy_SCB_SPI_ReadArray(), which are 1024/4096 bytes respectively. But I can see Rx FIFO holds a maximum of only 128 bytes. Is there a size limitation ?

I need to implement using PDL API's

Can you please help?

Thanks,

Binsy M S

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ncbs
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500 replies posted 50 likes received 250 sign-ins

Hi @BiM_4640481,

The size of Rx FIFO is not an issue when HAL APIs are used because they use interrupts to manage data transfer. Whenever data enters the RX FIFO, it is taken out. Hence the size of RX FIFO will not matter in that case.
 
Regards,
Nikhil
 
 

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3 Replies
ncbs
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500 replies posted 50 likes received 250 sign-ins

Hi @BiM_4640481,

Yes, RX FIFO can hold a maximum of 128 bytes.

Since large blocks of data have to be transferred, it is recommended to use DMA. 

Check out how to use DMA for SPI communication here: https://github.com/cypresssemiconductorco/mtb-example-psoc6-spi-master-dma

 

Hope this helps,
Nikhil

Hello Nikhil,

Thanks for the reply.

I have few more questions on this.

I have tried writing the same program using HAL API's. It works fine. I am able to read and write 1024 bytes of data.  HAL works on top of PDL right? Then why the size of Rx FIFO is not an issue in this case?

Thanks,

Binsy M S

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ncbs
Moderator
Moderator
Moderator
500 replies posted 50 likes received 250 sign-ins

Hi @BiM_4640481,

The size of Rx FIFO is not an issue when HAL APIs are used because they use interrupts to manage data transfer. Whenever data enters the RX FIFO, it is taken out. Hence the size of RX FIFO will not matter in that case.
 
Regards,
Nikhil