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BiM_4640481
Contributor

I am trying to integrate Toshiba flash driver code with Bootloader(version 1.x) code of PSoC6-43012 in MTB(version 2.2). The folder with driver files are kept under the project Bootloader. It resulted in errors as psoc6hal was not getting included in the build. So I added following statements in search.mk file of the project
CY_SEARCH_AVAILABLE_INCLUDES+=./libs/psoc6hal/include ./libs/psoc6hal/COMPONENT_PSOC6HAL/include ./libs/psoc6hal/COMPONENT_PSOC6HAL/include/pin_packages
CY_SEARCH_AVAILABLE_C_SOURCES+=./libs/psoc6hal/COMPONENT_PSOC6HAL/source ./libs/psoc6hal/COMPONENT_PSOC6HAL/source/pin_packages

Still I am getting errors:

Constructing build rules...
libs/psoc6make/make/core/build.mk:375: *** Incompatible source file type encountered while constructing explicit rule: ./libs/psoc6hal/COMPONENT_PSOC6HAL/source. Stop.
make: *** [libs/psoc6make/make/core/main.mk:414: secondstage_build] Error 2
"C:/Users/USER/ModusToolbox/tools_2.3/modus-shell/bin/make CY_MAKE_IDE=eclipse CY_MAKE_IDE_VERSION=2.2 CY_IDE_TOOLS_DIR=C:/Users/USER/ModusToolbox/tools_2.3 -j4 all" terminated with exit code 2. Build might be incomplete.

Can you please help to resolve this?

Thanks,

Binsy M S

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1 Solution
DheerajK_81
Moderator
Moderator

 Hello @BiM_4640481 ,

Are you referring to this code example? Please let me know which one so that I can guide you accordingly.

If the bootloader application is targeting the CM0p CPU, you need to make use of PSoC6 PDL APIs. PSoC6 HAL is not supported for CM0p CPU. 

You can find the PSoC6 PDL API reference guide here. Specifically, the APIs for SPI and GPIO can be found here and here respectively. 

Hope this helps 🙂

Regards,
Dheeraj

View solution in original post

5 Replies
DheerajK_81
Moderator
Moderator

Hello @BiM_4640481 ,

PSoC6HAL should be included in the build by default. You don't need to edit any internal files to include the HAL in the build. Please revert back your changes.

I think the error could be because of incompatible file types, probably in the flash driver files that you included.  The build system automatically discovers all .c, .h, .cpp, .s, .a, .o files in the application directory and subdirectories. Please check if you have some file types that aren't part of this list.

Regards,
Dheeraj

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BiM_4640481
Contributor

Thanks for the reply Dheeraj

I have already reverted back the changes.

When I tried to initialize the gpio's using cyhal_gpio_init(); ​I am getting undefined reference compilation error for all the HAL supported functions and parameters.In Makefile of Bootloader(version 1.x) project I saw the following lines

# Do not define PSOC6HAL component as HAL is not supported for CM0+

Can you please tell me if there is any way to add HAL support for the OTA MCUBoot application

If not, what is the suggested alternate to use it for the SPI for toshiba flash driver ?

 

Thanks,

Binsy M S

 

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DheerajK_81
Moderator
Moderator

 Hello @BiM_4640481 ,

Are you referring to this code example? Please let me know which one so that I can guide you accordingly.

If the bootloader application is targeting the CM0p CPU, you need to make use of PSoC6 PDL APIs. PSoC6 HAL is not supported for CM0p CPU. 

You can find the PSoC6 PDL API reference guide here. Specifically, the APIs for SPI and GPIO can be found here and here respectively. 

Hope this helps 🙂

Regards,
Dheeraj

View solution in original post

BiM_4640481
Contributor

Your inputs really helped. Yes I am referring to the same bootloader code example. Instead of QSPI NOR flash I want to use Toshiba NAND flash via SPI. As you suggested I used the SPI API's and GPIO API's for PDL layer. I tried to read the device Id of the flash chip before going to replace the existing driver with PDL SPI code. But the read device ID is all 0's.

BiM_4640481_0-1620740595974.png

 

I am posting here the code used .

/* Drive header files */
#include "cy_pdl.h"
#include "cy_scb_spi.h"
/*#include "cyhal.h"
#include "cycfg.h"
#include "cy_result.h"
#include "cy_retarget_io_pdl.h"
#include "cyhal_gpio_impl.h"
#include "cyhal_gpio.h"*/
#include <stdio.h>
#include "flash_qspi.h"
#define CY_RETARGET_IO_BAUDRATE (115200)
/* Flash PAL header files */
/*#ifdef CY_BOOT_USE_EXTERNAL_FLASH
#include "flash_qspi.h"
#endif*/

/* MCUboot header files */
#include "bootutil/image.h"
#include "bootutil/bootutil.h"
#include "bootutil/sign_key.h"
#include "bootutil/bootutil_log.h"

/* Added for Toshiba NAND flash */
#include "app_config.h"
#include "ndd_custom.h"

/* Allocate context for SPI operation */
cy_stc_scb_spi_context_t spiContext;
/* Populate configuration structure */

/* Master configuration */
cy_stc_scb_spi_config_t spiConfig =
{
.spiMode = CY_SCB_SPI_MASTER,
.subMode = CY_SCB_SPI_MOTOROLA,
.sclkMode = CY_SCB_SPI_CPHA0_CPOL0,
.oversample = 10UL,
.rxDataWidth = 8UL,
.txDataWidth = 8UL,
.enableMsbFirst = false,
.enableInputFilter = false,
.enableFreeRunSclk = false,
.enableMisoLateSample = true,
.enableTransferSeperation = false,
.ssPolarity = CY_SCB_SPI_ACTIVE_LOW,
.enableWakeFromSleep = false,
.rxFifoTriggerLevel = 0UL,
.rxFifoIntEnableMask = 0UL,
.txFifoTriggerLevel = 0UL,
.txFifoIntEnableMask = 0UL,
.masterSlaveIntEnableMask = 0UL,
};

/* Assign pins for SPI on SCB1: P12[0], P12[1], P12[2] and P11[1] */
#define SPI_PORT P12_0_PORT
#define SPI_MISO_NUM P12_1_NUM
#define SPI_MOSI_NUM P12_0_NUM
#define SPI_SCLK_NUM P12_2_NUM
#define SPI_SS_NUM P1_2_NUM

/* Assign divider type and number for SPI */
#define SPI_CLK_DIV_TYPE (CY_SYSCLK_DIV_8_BIT)
#define SPI_CLK_DIV_NUM (0U)
#define SPI_CLK_DIV_NUMBER 10


extern uint32_t OTA_Flash_Init(void);
/*******************************************************************************
* Macros
********************************************************************************/
/* Delay for which CM0+ waits before enabling CM4 so that the messages written
* to UART by CM0+ can finish printing. This delay is required since CM4 uses
* the same UART for printf redirect.
*/
#define CM4_BOOT_DELAY_MS (500UL)

/* Slave Select line to which the external memory is connected.
* Acceptable values are:
* 0 - SMIF disabled (no external memory)
* 1, 2, 3, or 4 - slave select line to which the memory module is connected.
*/
#define QSPI_SLAVE_SELECT_LINE (1UL)

/******************************************************************************
* Function Name: do_boot
******************************************************************************
* Summary:
* This function extracts the image address and enables CM4 to let it boot
* from that address.
*
* Parameters:
* rsp - Pointer to a structure holding the address to boot from.
*
******************************************************************************/
static void do_boot(struct boot_rsp *rsp)
{
uint32_t app_addr = (rsp->br_image_off + rsp->br_hdr->ih_hdr_size);

BOOT_LOG_INF("Starting User Application on CM4. Please wait...");
Cy_SysLib_Delay(CM4_BOOT_DELAY_MS);
Cy_SysEnableCM4(app_addr);

while (true)
{
__WFI();
}
}


/******************************************************************************
* Function Name: main
******************************************************************************
* Summary:
* System entrance point. This function initializes peripherals, initializes
* retarget IO, and performs a boot by calling the MCUboot functions.
*
* Parameters:
* void
*
* Return:
* int
*
******************************************************************************/
#if 0
int main(void)
{
struct boot_rsp rsp;

/* Initialize system resources and peripherals.
* Do not call init_cycfg_system() as the system clocks and resources will
* be initialized by CM4.
*/
init_cycfg_clocks();
init_cycfg_peripherals();
init_cycfg_pins();

/* Certain PSoC 6 devices enable CM4 by default at startup. It must be
* either disabled or enabled & running a valid application for flash write
* to work from CM0+. Since flash write may happen in boot_go() for updating
* the image before this bootloader app can enable CM4 in do_boot(), we need
* to keep CM4 disabled. Note that debugging of CM4 is not supported when it
* is disabled.
*/
#if defined(CY_DEVICE_PSOC6ABLE2)
if (CY_SYS_CM4_STATUS_ENABLED == Cy_SysGetCM4Status())
{
Cy_SysDisableCM4();
}
#endif /* #if defined(CY_DEVICE_PSOC6ABLE2) */

/* Enable interrupts */
__enable_irq();

/* Initialize retarget-io to redirect the printf output */
cy_retarget_io_pdl_init(CY_RETARGET_IO_BAUDRATE);

BOOT_LOG_INF("MCUboot Bootloader Started");

#ifdef CY_BOOT_USE_EXTERNAL_FLASH
/* Initialize QSPI NOR flash using SFDP. */
cy_rslt_t result = qspi_init_sfdp(QSPI_SLAVE_SELECT_LINE);

if(CY_SMIF_SUCCESS == result)
{
BOOT_LOG_INF("External Memory initialized using SFDP");
}
else
{
BOOT_LOG_ERR("External Memory initialization using SFDP FAILED: 0x%02x", (int)result);
}

if(CY_SMIF_SUCCESS == result)
#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
{
if (boot_go(&rsp) == 0)
{
BOOT_LOG_INF("User Application validated successfully");
do_boot(&rsp);
}
else
{
BOOT_LOG_INF("MCUboot Bootloader found no bootable image") ;
}
}

return 0;
}
#endif

GPIO_PRT_Type *Port_11 = GPIO_PRT11;
int Port_11_Pin = 1;
GPIO_PRT_Type *Port_12 = GPIO_PRT12;
static int Port_12_Pin = 3;
GPIO_PRT_Type *Port_1 = GPIO_PRT1;
static int Port_1_Pin = 2;

void Flash_pins_init(void)
{
/*cy_rslt_t result;
result = cyhal_gpio_init(mSPI_SS, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, 1);
result = cyhal_gpio_init(Flash_Hold, CYHAL_GPIO_DIR_OUTPUT,CYHAL_GPIO_DRIVE_STRONG, 1);
cyhal_gpio_write(mSPI_SS, 1);
cyhal_gpio_write(Flash_Hold, 1);*/

/* PDL GPIO API's */
Cy_GPIO_Pin_FastInit(Port_11, Port_11_Pin, CY_GPIO_DM_STRONG, 1, HSIOM_SEL_GPIO); //mSPI_SS ,HSIOM_SEL_GPIO=0 means GPIO controls 'out'
Cy_GPIO_Pin_FastInit(Port_12, Port_12_Pin, CY_GPIO_DM_STRONG, 1, HSIOM_SEL_GPIO); //Flash_Hold
Cy_GPIO_Write(Port_11, Port_11_Pin, 1);
Cy_GPIO_Write(Port_12, Port_12_Pin, 1);
}

int main(void)
{
struct boot_rsp rsp;
uint8_t txBuffer[3];
uint8_t rxBuffer[2];
/* Initialize txBuffer with command to transfer */
txBuffer[0] = 0x9F;
txBuffer[1] = 0x00U;
txBuffer[2] = 0x01U;

/* Initialize system resources and peripherals.
* Do not call init_cycfg_system() as the system clocks and resources will
* be initialized by CM4.
*/
init_cycfg_clocks();
init_cycfg_peripherals();
init_cycfg_pins();

/* Certain PSoC 6 devices enable CM4 by default at startup. It must be
* either disabled or enabled & running a valid application for flash write
* to work from CM0+. Since flash write may happen in boot_go() for updating
* the image before this bootloader app can enable CM4 in do_boot(), we need
* to keep CM4 disabled. Note that debugging of CM4 is not supported when it
* is disabled.
*/
#if defined(CY_DEVICE_PSOC6ABLE2)
if (CY_SYS_CM4_STATUS_ENABLED == Cy_SysGetCM4Status())
{
Cy_SysDisableCM4();
}
#endif /* #if defined(CY_DEVICE_PSOC6ABLE2) */

/* Enable interrupts */
__enable_irq();

/* Initialize retarget-io to redirect the printf output */
cy_retarget_io_pdl_init(CY_RETARGET_IO_BAUDRATE);

BOOT_LOG_INF("MCUboot Bootloader Started");

#ifdef CY_BOOT_USE_EXTERNAL_FLASH
/* Initialize the flash pins */
Flash_pins_init();
cy_en_scb_spi_status_t result;
result = Cy_SCB_SPI_Init(SCB6, &spiConfig, &spiContext);
if(result == CY_SCB_SPI_SUCCESS)
{
BOOT_LOG_INF("Cy_SCB_SPI_Init success\n");
}
else
{
BOOT_LOG_INF("Cy_SCB_SPI_Init failed\n");

}

/* Connect SCB1 SPI function to pins */
Cy_GPIO_SetHSIOM(SPI_PORT, SPI_MISO_NUM, P12_1_SCB6_SPI_MISO);
Cy_GPIO_SetHSIOM(SPI_PORT, SPI_MOSI_NUM, P12_0_SCB6_SPI_MOSI);
Cy_GPIO_SetHSIOM(SPI_PORT, SPI_SCLK_NUM, P12_2_SCB6_SPI_CLK);
Cy_GPIO_SetHSIOM(P1_0_PORT, Port_1_Pin, P1_2_GPIO);//P11_1_SCB5_SPI_SELECT0);

/* Configure SCB6 pins for SPI Master operation */
Cy_GPIO_SetDrivemode(SPI_PORT, SPI_MISO_NUM, CY_GPIO_DM_HIGHZ);
Cy_GPIO_SetDrivemode(SPI_PORT, SPI_MOSI_NUM, CY_GPIO_DM_STRONG_IN_OFF);
Cy_GPIO_SetDrivemode(SPI_PORT, SPI_SCLK_NUM, CY_GPIO_DM_STRONG_IN_OFF);
Cy_GPIO_SetDrivemode(P1_0_PORT, Port_1_Pin, CY_GPIO_DM_STRONG_IN_OFF);


/* Connect assigned divider to be a clock source for SPI */
Cy_SysClk_PeriphAssignDivider(PCLK_SCB6_CLOCK, SPI_CLK_DIV_TYPE, SPI_CLK_DIV_NUM);

/* SPI master desired data rate is 1 Mbps.
* The SPI master data rate = (clk_scb / Oversample).
* For clk_peri = 50 MHz, select divider value 5 and get SCB clock = (50 MHz / 5) = 10 MHz.
* Select Oversample = 10. These setting results SPI data rate = 10 MHz / 10 = 1 Mbps.
*/
Cy_SysClk_PeriphSetDivider (SPI_CLK_DIV_TYPE, SPI_CLK_DIV_NUMBER, 4UL);
Cy_SysClk_PeriphEnableDivider(SPI_CLK_DIV_TYPE, SPI_CLK_DIV_NUMBER);
/* Enable SPI to operate */
Cy_SCB_SPI_Enable(SCB6);

Cy_GPIO_Write(Port_11, Port_11_Pin, 0);

/* Master: start a transfer. Slave: prepare for a transfer. */
//Cy_SCB_SPI_WriteArrayBlocking(SCB6, txBuffer, sizeof(txBuffer));
int ret = Cy_SCB_SPI_Write(SCB6,0x9F);
BOOT_LOG_INF("Cy_SCB_SPI_Write returned : %d\n", ret);

int ret = Cy_SCB_SPI_Write(SCB6,0xFF);
BOOT_LOG_INF("Cy_SCB_SPI_Write returned : %d\n", ret);
/* Blocking wait for transfer completion */
/* while (!Cy_SCB_SPI_IsTxComplete(SCB6))
{
}*/
BOOT_LOG_INF("SPI Transfer Complete\n");

/* Read the device id*/
Cy_SCB_SPI_ReadArray(SCB6, &rxBuffer, 2);

BOOT_LOG_INF("device id = %d %d\n", rxBuffer[0], rxBuffer[1]);

/* Initialize SPI NAND flash */
/*cy_rslt_t result = OTA_Flash_Init();

if(CY_SMIF_SUCCESS == result)
{
BOOT_LOG_INF("External Memory initialized using SFDP, result = %d\n", result);
}
else
{
BOOT_LOG_ERR("External Memory initialization using SFDP FAILED: 0x%02x", (int)result);
}*/

Cy_GPIO_Write(Port_11, Port_11_Pin, 1);

if(CY_SMIF_SUCCESS == result)
#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
{
if (boot_go(&rsp) == 0)
{
BOOT_LOG_INF("User Application validated successfully");
do_boot(&rsp);
}
else
{
BOOT_LOG_INF("MCUboot Bootloader found no bootable image") ;
}
}

return 0;
}

Your inputs will be of great help.

Thanks,

Binsy M S

 
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