MCU & PSoC

I have an Psoc63 as BLE 5 central and three PSoC 4200 as BLE 4.2 peripheral. After a successful discovery from central using whitelist I try to connect to one of the three peripheral using his address.  Unexpectedly the central was connected with a peripheral with different address!!!!! Also I try an unexisting address and again it was connected with a random peripheral with different address. Maybe the issue arise from the BLE 4.2 peripherals.

I will appreciate your help to this

Hi,

Can we just implement TPS25982 block diagram to PSoC5LP MCU. I am attaching the link for datasheet of TPS25982 and the functional block diagram

 https://www.ti.com/lit/ds/symlink/tps25982.pdf?ts=1611299035488&ref_url=https%253A%252F%252Fwww.google.com%252F

Page No:18

Please do let me know in full brief about the different blocks.

Hello，

I am learning PSoC6 from the PSoC6 101 video tutorial series . From the PSoC 6 - 1-1-Introduction Alan Hawse told that PSoC6 chapters contains 4 parts.
I have downloaded the 1st,2nd and 3rd parts. And the last part is "connecting with WiFi & Cloud services".And I do not know the hyperlink of it. How can I get it?
Thanks in advance.

Hello,

I am using PSOC6 PROTOTYPEKIT BOARD 。
I am using a Verilog file for DS18B20 testing (I got it from a test in Altera Cyclone IV and it works well). But the file cannot be built in PSOC Creator 4.3
The Screenshot in PSOC Creator 4.3.

The errors occurred in building
It seems that the PSOC Creator 4.3 cannot interpret the line 171

Can't handle expression 'Z' in the final equation for 'org_data(0)'.

And I do not know how to solve it.

And I wonder whether the Verilog syntax in PSOC Creator 4.3 is just a subet of the Verilog syntax in general.

Thanks in advance.

Good morning,

how you can see on attached file, I would to pilot 10 7-segment displays with LED_Driver block.

I can't use a second LED_Driver because the 7-segment are commons and Creator give me an error.

Is there a way to use LED_Driver block with 10 commons?

Thanks for all your helps.
Mattia Scricciolo

Hi

I am using PSoC-6 as SPI slave to send data to master (PC).

Description of Cy_SCB_SPI_WriteArrayBlocking() says: When in the slave mode, writing data into the TX FIFO does not start an SPI transfer. The data is loaded in the TX FIFO and will be sent to the master on its request.

Does the PSoC slave SPI sends data once it receives the clock from the bus master ? or does it respond when the master asserts the slave_select ?

thanks

We are using CY_BLE_EVT_GAP_DEVICE_DISCONNECTED to know if the peripheral got disconnected. On CY_BLE_EVT_GAP_DEVICE_DISCONNECTED we perform connection cleanup, but we noticed on one time the peripheral disconnected but it seems like we missed or didn't get CY_BLE_EVT_GAP_DEVICE_DISCONNECTED.

Is it expected not to get CY_BLE_EVT_GAP_DEVICE_DISCONNECTED event when device disconnect? Is there way to manually check if BLE stack properly disconnected?

Hi,

I have been working to implement a circuit on PSoC5LP MCU as the PSoC5 LP MCU supports both analog and digital peripherals but in analog we have 4 comparators and 4op-amps, what in the situation if we require MOSFET in the situation, then what should be my approach? 

Anyone Please do let me know, waiting for your reply.

Thanks & Regards,

Prateek

Hello,

I have created a trackpad using the PSoc 4 MCU that will be utilized as a BLE Mouse to control a cursor on a computer screen. I would also like to collect information on the position of the finger on the trackpad. Up until now, I have used the Launch tuner to log this position data, however, I would ideally like this to be done on a computer software. How can change the provided BLE HID Mouse code by Cypress to read information related to the position of the finger on the trackpad rather than the displacement?

Thank you,

I'm looking to interface external memory with one of the PSoC 6 chips. Our application has large storage requirements (to the tune of around 2-4 gigabytes), so SPI NAND is off the table. Since our use case needs bluetooth and possibly USB, we were looking at the PSoC 63 line, but these chips don't seem to support e.MMC memory, which has raised a few questions?

Is there a (relatively) easy way to interface with raw unmanaged NAND using the PSOC 6 line, or to use e.MMC with PSoC 63? Alternatively, is anyone familiar with any chips that could serve as an intermediary SPI Controller to go between a raw NAND chip and the PSoC MCU, or any other way to work around this? 

The PSoC 62 chips seem to have support for SDHC communication, but to use bluetooth and USB I believe we would need one of the CY8C624A/8 chips with two SDHC interfaces. 

Would appreciate any insight on this, as we'll otherwise need to move away from the PSoC chips and start looking at alternatives.