MCU & PSoC

I am using an CY8C21534-24PVXI part using a UART block version 5.3 Have it set up to use both tx and rx interrupts, modified boot.tpl accordingly. Am NOT using the command buffer feature, have my own fifos. The transmitter works fine, but I can never get an Rx interrupt. Have no idea why this is, compiles fine, schematic editor looks fine just like the other examples. Scoped it and data is getting to the pin so this is not the issue. So..what's missing here, does this actually work? thanks ken Show Less

Hi,

 

I am using Capsens module V4.0.

I am using Widget Buttons for my application In this, I found that sometimes it detects the false senses means it sens when I do not even touch the button..

In my application I use Enable all 13 buttons using CapSense_SetParam(CapSense_WDGT_ENABLE0_PARAM_ID, 8191); and after complete the process I disable only 12 buttons CapSense_SetParam(CapSense_WDGT_ENABLE0_PARAM_ID, 4096);  because I use the 13th button for touch detection only this performs at every operation.

Why this false detection is happening? is it because of the calling CapSense_SetParam(CapSense_WDGT_ENABLE0_PARAM_ID, 8191) ? 

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I have an application where, if I am in Bootloader mode and nothing has happened for about 60sec, I want to go into Hibernate mode (my device is battery powered, and I want to ensure that it doesn't sit in Bootloader mode indefinitely if something goes wrong and then drains my battery).

I can use a Timer to force the Bootloader into Hibernate mode, but I can't seem to get it to come back out of Hibernate using an interrupt on an external GPIO.

I am using a similar arrangement, using a signal on a GPIO, in the Application code to boot the device out of Hibernate mode, and this works perfectly.  But it doesn't seem to work when in Bootloader mode.

Has anyone tried this?  Is there something about being in Bootloader mode and then going into Hibernate that would prevent the 'exit from Hibernate via GPIO trigger' functionality from working?

Cheers,

Mike

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Dear Cyprerss/Infineon Support,

Wrong configuration for TX-Enable pin (RS-485 Support) is generated using the Device Configurator 3.0.

I had a problem using the configuration generated with that tool. If I select  a TX-Enable pin it generates a configuration like this:

#ifndef ioss_0_port_3_pin_3_HSIOM

#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO

#endif

 

But it must be like this to have a signal coming from CTS pin:

 

#ifndef ioss_0_port_3_pin_3_HSIOM

#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_ACT_6

#endif

 

Regards,

Gintaras

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How can I read the unique id from PSoC 5LP devices within ppcli?

Refering to PSoC 5LP Registers TRM and according to code generated (CyLib.c and cydevice_trm.h the unique is stored at addresses like 0x4900 010x (with exception of CYREG_MLOGIC_REV_ID referring to 0x400046ec).

How can I retrieve these values for production purposes before flashing user code (i.e. without executing user code)?

I tried things like PSoC3_ReadRow 0x4900 0x0n 0x00 (n = 0..F) but the given results do not seem to contain right values.

Is there a function for reading data from random (existing) addresses in address space?

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Hi,

In a PsoC4 project attached below we demonstrate a PWM compare register write bug.

It appears like if reg is written by the CPU at the same time as TC occurs pwm output is forced high for the entire period, and within the next cycle the latest compare value is in effect.

We have tried combinations with RegSwap, which also appears buggy, at certain occasions it swapped immediately.

Looking forward to hearing you and your explanation and best work-around.

Kind regards,
Uros

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Hello,

I have been requested the marking information of PSoC4100S.
I refer the document of CYPRESS MARKING FORMAT JANUARY 2020 (https://www.cypress.com/file/41321/download) , but specified information of WLCSP 35L is different from the actual IC marking.

Please confirm my understanding and provide the correct information.(see attached file)

MPN: CY8C4146FNI-S433 (WLCSP 35L)

Best regards,
Naoaki Morimoto

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