Version: **

The original version of the firmware programmed on the CYPD3177 EZ-PD^™ BCR devices older than date code (YYWW format – last two digits of the year, and two digits of the work week) “2047” is version 3.0C. The updated firmware version that the CYPD3177 devices have with the date code “2047” or later, is version 4.05. The updates incorporated in firmware version 4.05 are listed in Table 1.

Table 1. List of updates incorporated in EZ-PD^TM BCR device (CYPD3177) firmware version 4.05

Table 2. FLIP Pin Pull-Up Resistor value and the Data Capability Bit Being Presented

Version: **

Question:

Why is the newer configuration programmed to USB-Serial device not updated even after power cycling the USB port?

Answer:

Figure 1 shows a self-powered scenario, where the device VBUS/VCC pin is powered from the VBUS of the USB connector and VDDD/VCCIO pin of the USB-Serial device is not directly or indirectly powered from the VBUS of USB connector. 

In the above scenario, when the USB-Serial device is disconnected from the host after programming, the internal core of USB-Serial device, which is powered through VDDD/VCCIO will still retain its previous configuration.

Note:  VCC and VCCIO corresponds to part numbers CY7C65213 and CY7C65213A.

            VBUS and VDDD corresponds to part numbers CY7C65211, CY7C65211A, CY7C65215, and CY7C65215A

Figure 1. Self-powered Configuration Scenario

For the newer programmed configuration to be updated, one of the following conditions should be met:

1. The USB-Serial device VDDD/VCCIO pin should be power cycled.
2. The USB-Device must be reset by asserting its Reset pin low for a minimum of 1 us.
3. The USB-Serial Device must be reset from the host to which it is connected by using the Reset Device option in the USB-Serial Configuration utility (see Figure 2) or by issuing a CyResetDevice() call from an host application from which the device is accessed (see the Cypress USB-Serial API Documentation from the USB-Serial SDK).

Figure 2. USB-Serial Configuration Utility Reset Device Option

So, when a USB-Serial Device is in self-powered configuration as shown in Figure 1, that is, when the VDDD/VCCIO is powered using an internal sourcem and the internal source remains active when the board is not connected to host, the newly programed configuration will not be updated even after the USB is reconnected, until the device is reset.

Version: **

The CCG_FLIPPED_FET_CTRL macro swaps the provider FET and the consumer FET. In other words, it controls the consumer FET by PCTRL and the provider FET by CCTRL. The FETs are swapped because VBUS_IN_DISCHARGE is connected to Type-C VBUS according to the power bank design requirement.

VBUS_IN_DISCHARGE has an internal LDO capable of powering the chip, while the PFET has an internal pull-up to this side. However, the VBUS_C_MON pin has no LDO capability.

Therefore, in designs that need dead battery support, the LDO must be on the Type-C side. That is why in such designs, VBUS_IN_DISCHARGE pin is connected to the Type-C VBUS and the VBUS_C_MON pin is connected to the VBUS source. Because VBUS_IN is flipped with VBUS_C_MON, the FETs also need to be swapped i.e., PCTRL should be used for consumer FET and CCTRL should be used for provider FET. This is because of the pull-up of the PFET to the VBUS_IN_DISCHARGE pin; therefore, it is called “FLIPPED_FET”.

When this macro is enabled, it implies that VBUS_IN_DISCHARGE is connected to Type-C VBUS. Therefore, the VBUS_IN resistor divider is used to monitor Type-C VBUS.

The diagram shown below depicts the provider fet and consumer fet connections in power bank applications.

Refer to the Power SDK (https://www.cypress.com/documentation/software-and-drivers/ez-pd-ccgx-power-software-development-kit) for the implementation of the CCG_FLIPPED_FET_CTRL macro.

Version: **

CCG3PA is Cypress’s USB Type-C Controller targeted for power adapter and power bank applications. CCG3PA supports various fault protections schemes such as over-voltage, under-voltage and over-current protection. The chip can also support over-temperature protection with an external thermistor on a GPIO routed to internal ADC.

The following fault protection schemes can be implemented in CCG3PA. When a fault is encountered, the port disable state is invoked to prevent the system from damage. The following occur in the port disable state:

• Type-C port terminations from CC and D+/- lines are removed.
• Provider/Consumer FETs based on current port role are turned off.

1.1  Overvoltage Protection (OVP)

OVP is implemented for both Type-C port power roles (source and sink). Overvoltage is a fault condition when VBUS exceeds a preset level. During PD negotiation between port partners, the operational VBUS level is negotiated. After the PD negotiation, CCG3PA monitors VBUS in both source and sink roles. If VBUS exceeds the pre-defined threshold, OVP condition is executed.

1.1.1 Firmware parameters

• OV_ENABLE: Enable or disable OVP.
• OV_THRESHOLD: The percentage threshold above VBUS to be treated as an OV fault.
• OV_DEBOUNCE: The time duration before declaring an OV fault.
• OV_RETRY_COUNT: Specifies the number of tries before disabling the port.

1.1.2 Implementation

CCG3PA has a programmable resistor divider and a dedicated comparator for detecting OVP. VBUS is divided using the resistor divider and is routed to the comparator while the other terminal of the comparator is connected with a reference voltage. If VBUS exceeds the threshold, the comparator trips and an interrupt is generated.

As soon as the OV condition is signaled, the firmware disables the port and re-enables it after a pre-defined time. If the OV condition still exists, it goes through the disable-enable cycle again. This is repeated for a specific number of retries after which the port is temporarily disabled; it can be re-enabled through a hard reset/power cycle or by disconnecting/reconnecting the port partner.

1.2 Undervoltage Protection (UVP)

UVP is implemented only for the “source” port power role. UVP is implemented only for the “source” port power role. Undervoltage is a fault condition where VBUS drops below the operational level. After the PD negotiation between port partners, CCG3PA monitors the VBUS level; if VBUS falls below the threshold, a UVP condition is declared.

1.2.1 Firmware Parameters

• UV_ENABLE: Enable or disable UVP.
• UV_THRESHOLD: The percentage threshold below VBUS to be treated as a UV fault.
• UV_DEBOUNCE: Time duration before declaring a UV fault.
• UV_RETRY_COUNT: Specifies the number of tries before disabling the port.

1.2.2 Implementation

Similar to OVP, CCG3PA has a dedicated comparator to detect UVP.

The resistor divider provides the divided VBUS which is routed to the comparator while the other terminal of the comparator is the reference voltage. If VBUS drops below the UVP threshold, the comparator trips and an interrupt is generated.

On receiving the UVP signal, the firmware disables the Type-C port and re-enables it after a specified time interval. This cycle of disable-enable is repeated for a specified number of retries after which the port is completely disabled; it can be enabled through a hard reset/power cycle or by disconnecting/reconnecting the sink.

1.3 Overcurrent Protection (OCP)

OCP is implemented only for the “source” port power role.

Overcurrent is a fault condition when the current consumption is larger than intended.

During power contract negotiation, current is negotiated between port partners. CCG3PA monitors the current levels, and if it exceeds the threshold level, an OCP condition is declared.

1.3.1 Firmware Parameters

• OC_ENABLE: Enable or disable OC protection.
• OC_THRESHOLD: The percentage threshold above nominal operating current to be treated as an OC fault.
• OC_DEBOUNCE: The time duration before declaring an OC fault.
• OC_RETRY_COUNT: Specifies the number of tries before the port is shut down. A retry count of 255 implies infinite retries.

1.3.2 Implementation

CCG3PA has a dedicated comparator and a low-side current sense amplifier (LSCSA) for OCP detection. An external sense resistor Rsense is placed in series with load.

The Rsense resistor is placed across the CSP pin and GND, while LSCSA senses Vsense across Rsense. This is amplified and routed to the comparator where it is compared with the reference voltage. The reference voltage and amplifier gain are related to the target current.

When the current consumption exceeds the threshold, the comparator trips and the OC fault is signalled.

On receiving the OC fault signal, the firmware disables the Type-C port and re-enables it after a specified time interval. This cycle of disable-enable is repeated for a specified number of tries after which the port is completely disabled and can be enabled only through a hard reset/power cycle or by disconnecting/reconnecting the port partner.

1.4 Overtemperature Protection (OTP)

OTP is implemented for both Type-C port power roles (source and sink). CCG3PA requires an external thermistor to enable this protection.

Overtemperature is a fault condition when the temperature of the system exceeds a pre-defined threshold value.

1.4.1 Firmware Parameters

• OT_ENABLE: Enable or disable OTP.
• OT_THERM_TYPE: Specifies whether a Negative Temperature Co-efficient (NTC) or Positive Temperature Co-efficient (PTC) thermistor is being used.
• OT_VOLT_NOMINAL: GPIO voltage at nominal room temperature.
• OT_VOLT-CUTOFF: GPIO voltage at cut-off temperature.
• OT_VOLT_RESTART: GPIO voltage at restart temperature.
• OT_DEBOUNCE: Specifies the time interval before declaring an OT fault.
• OT_POLL_PERIOD: Periodic polling interval for OT fault.

1.4.2 Implementation

CCG3PA uses an external thermistor to monitor system temperature. A fixed resistor is used along with the thermistor to build a resistor divider circuit. The voltage across the thermistor is routed to CCG3PA over a GPIO, and sensed through the internal ADC.

Reference: See the CCGx Power SDK User Guide.

Version: **

To detect the state of PMODE pins, the FX3 bootloader enables internal pull-up and pull-down resistors on PMODE lines in the sequence as follows:

1. The bootloader initially pulls up all the PMODE pins internally to HIGH voltage with 50-kΩ resistors (see section Digital I/Os of FX3 datasheet). After waiting for 5 µs, the bootloader samples the state of the PMODE pins.

2. The bootloader removes the pull-up on PMODE lines and then pulls down the PMODE lines to the LOW voltage with 10-kΩ resistors (see page 13 of FX3 datasheet). Again, it waits for 5 µs and then samples the state of the PMODE pins. After this, the internal pull-downs are removed.

This process is repeated on every connection/reset of the device.

The bootloader checks whether a PMODE pin is floating. For this, it uses the sampled states of the PMODE lines when the pull-up and pull-down resistors were enabled.

Note: See Table 8 - DC specifications of the FX3 datasheet to understand the range of voltages that are interpreted as HIGH / LOW corresponding to the power domain voltage of a particular I/O.

If a PMODE pin is floating:

When placing an internal pull-up, the voltage on that pin will be HIGH. When an internal pull-down is placed on that pin, the voltage on that pin will be LOW. This change in the voltage level upon changing the internal pull-up and pull-down resistors is used by the bootloader to detect whether the pin is floating.

If a PMODE pin is pulled HIGH externally or supplied with a HIGH voltage externally:

When an internal pull-up is enabled on that pin by the bootloader, the voltage on that pin will be HIGH itself. Next, when an internal pull-down is enabled, a voltage divider is formed at that pin (external resistor and the internal 10kpull-down). Here, while choosing the external resistor, ensure that the voltage at that pin does not fall into the LOW level. If it falls into the LOW level, the bootloader will interpret that pin as floating.

If a PMODE pin is pulled down externally:

When an internal pull-up resistor is placed on that pin by the bootloader, a voltage divider is formed (50k internal pull-up and the external pull-down resistor). Here also, while choosing the external resistor, ensure that the voltage at that pin does not fall into the HIGH level. Next, when the bootloader places an internal pull-down resistor on that pin, the voltage on that pin will be LOW itself. Thus, if the voltage on the pin when the bootloader placed an internal pull-up resistance fell into the HIGH level, the bootloader would have detected the pin as floating.

The recommended value for external pull-up and pull-down resistors on PMODE lines is 10k.

Effect of dip and spike in PMODE voltage levels when the FX3/CX3 device is connected to host or reset.

See the following discussion thread in the Developer Community:

https://community.cypress.com/thread/50671

As mentioned earlier, the bootloader enables internal pull-up and pull-down resistors for detecting the state of PMODE pins. These pull-up and pull-down resistors enabled by the bootloader internally cause the dip and spikes seen on the PMODE lines. It will not affect the functionality of these pins.

Version: **

See Section 6.8- USB 3.0 and USB 2.0 Function Coordination  of the FX3 Technical Reference Manual (TRM) for the procedure used by FX3 firmware for USB connection negotiation.

From the datasheet of Texas Instruments TUSB501, after power up, the TUSB501 device periodically performs receiver detection on the Tx pair. If it detects a SuperSpeed USB receiver, it enables Rx termination, and the TUSB501 is ready to redrive.

Thus, when the FX3 device is connected to the re-driver, the re-driver detects FX3 as a receiver and enables its terminations. Similarly, FX3 also turns on its USB 3.0 PHY and starts USB 3.0 receiver detection. Because the re-driver is active all the time, FX3 detects the re-driver. If the re-driver is connected to the host using USB 2.0 cables, the FX3 device will wait for USB 3.0 enumeration packets indefinitely and does not fall back to USB 2.0 mode. Because of this, the device will neither enumerate in USB 3.0 nor in USB 2.0 mode. This is an expected behavior according to Section 6.8 - USB 3.0 and USB 2.0 Function Coordination of the FX3 TRM because receiver detection was successful.

Do the following to try USB 3.0 enumeration and to fall back to USB 2.0 enumeration if it fails:

1. Declare a timer structure (CyU3PTimer) globally. See the FX3 API guide for more details.

2. Create a timer using CyU3PTimerCreate(). This API can be called immediately after calling CyU3PConnectState(CyTrue, CyTrue) for USB 3.0 enumeration. Set the last parameter (timerOption) of CyU3PTimerCreate() to CYU3P_AUTO_ACTIVATE to start the timer immediately; if not, start the timer by using CyU3PTimerStart(). See FX3 API guide for more details on these APIs.

The default value of one timer tick is 1 ms. The timeout while creating the timer should be sufficient to ensure that USB 3.0 enumeration happens without errors.

3. Check whether the CY_U3P_USB_EVENT_SETCONF event is received before the timer expires. The successful reception of CY_U3P_USB_EVENT_SETCONF before the timer expiry indicates that the USB 3 enumeration was successful. In this case, when CY_U3P_USB_EVENT_SETCONF event is received, stop the timer using CyU3PTimerStop().

4. If the CY_U3P_USB_EVENT_SETCONF event is not received before the timer expires, the callback function that was provided while calling CyU3PTimerCreate() will be executed. This means that USB 3 enumeration was not successful. Therefore, inside the callback function, do the following to enumerate the device in USB 2.0 mode:

a. Disable the USB connection by using CyU3PConnectState(CyFalse, CyTrue);.

b. Provide a small delay by using CyU3PThreadSleep (100);.

c. Attempt USB 2.0 enumeration by using CyU3PConnectState (CyTrue, CyFalse);.

The firmware that comes along with AN75779 – How to Implement an Image Sensor Interface Using EZ-USB FX3 in a USB Video Class (UVC) Framework can be used as a reference for implementing timer operations.

Version: **

Question: How do I check if the FX3 bootloader is running using the Linux SDK or what is the equivalent of the IsBootLoaderRunning() function in FX3 Linux SDK?

Answer:

FX3 Linux SDK does not have a specific function to check if the FX3 bootloader is running.

But, the functionality can be achieved using the vendor command 0xA0 through control transfer (cyusb_control_transfer() function).

The vendor command 0xA0 is implemented in FX3 Bootloader for firmware download and upload, and the same command can be used to check if the FX3 is in bootloader mode.

A single byte IN control transfer with request code 0xA0 is initiated. If the control transfer succeeds and returns a byte, then the bootloader in running.

Control transfer parameters:

bRequest = 0xA0;

bmRequestType = 0xC0;

wValue = 0x0000;

wIndex = 0x0000;

wLength = 1;

Control Transfer function prototype from FX3 Linux SDK:

int cyusb_control_transfer (cyusb_handle *h, unsigned char bmRequestType,

unsigned char bRequest, unsigned short wValue,

unsigned short wIndex, unsigned char *data,

unsigned short wLength, unsigned int timeout);

Sample Code:

int num = cyusb_open();

printf("number of devices = %d\n", num);

if (num <= 0)

return -1;

cyusb_handle *h = cyusb_gethandle(0);

unsigned short vid = cyusb_getvendor(h);

unsigned short pid = cyusb_getproduct(h);

printf("vid = %04x,  pid  = %04x\n" , vid, pid);

unsigned char bmReqType = 0xC0;

unsigned char bRequest = 0xA0;

unsigned short wValue = 0x0000;

unsigned short wIndex = 0x0000;

unsigned short wLength = 1;

unsigned char buf_data[1] = {0};

unsigned int timeout = 5000;

int retval = cyusb_control_transfer (h, bmReqType, bRequest, wValue, wIndex, buf_data, wLength, timeout);

if(retval>0)

printf("fx3 bootloader running\n");

else

printf("fx3 bootloader not running\n");

Community Translated by NoTa_4591161             Version: **

Translation - English: USB-Serial: Hardware Design Schematic Checklist - KBA231249

質問：
USB-シリアルブリッジコントローラーを正常に動作させるために回路図を設計する際に確認する必要がある項目は何でしょうか？

回答：
以下は、USBシリアルブリッジコントローラーの回路図設計を設計する際に従う必要がある重要な項目のリストです。

1. 表1に従って、すべての電源ピンのVCC（またはVBUS）およびVCCIO（またはVDDD）に適切な電圧レベルが供給されていますか？

2. 1.71 V £VDDD / VCCIO£1.89 Vの場合、VCCDはVDDD / VCCIOに短絡していますか？

VDDD / VCCIO> 2 Vの場合、VCCD / VCCIOピンに接続された1 uFのデカップリングコンデンサは？

3.フェライトビーズL1がUSBコネクタのVBUSピンに接続されていますか？

USBホストからノイズを分離するには、フェライトビーズをUSBコネクタに接続する必要があります。それぞれのUSBシリアルコントローラーのDVK/RDK回路図（CYUSBS232 RDK、CYUSBS234 DVK、CYUSBS236 DVK）をご参照願います。

4. USBシリアルデバイスのVBUS / VCCピンに接続されている0.1 uFのデカップリングコンデンサは、ICの近くにありますか？

5.デカップリングコンデンサ0.1 uFと4.7 uFは、ICの近くのUSB-SerialデバイスのVCCIO/VDDDピンに接続されていますか？

これにより、低周波および高周波のノイズが除去されます。

6. USB-シリアルブリッジコントローラーには、2.2 kVのESD保護が組み込まれています。2.2 kVを超える保護のために、ESDダイオードをVBUS/VCC、USBDP、およびUSBDMラインに接続しましたか？

7. リセット（XRES）ピンは、抵抗を使用して外部でHighにプルされていますか？

USB-シリアルデバイスは、アクティブLowの外部リセットをサポートしています。USB-シリアルコントローラーをリセットするには、XRESピンを最低1 usの間Lowに保持する必要があります。

図1に示すように、nXRESピンは、外部抵抗を介してVDDD（またはVCCIO）に、および外部コンデンサ（最小1 µsの時定数）を介してグランド（GND）に接続できます。1µsのパルス幅要件を満たすには、RとCの推奨値は、それぞれ100Ωと0.01 µFです。

図1 . USB-シリアルブリッジコントローラーのリセット回路の例

GPIO：

8. すべての入力ピンは、10kΩのプルアップ（またはプルダウン）抵抗を使用してHigh（またはLow）にプルされていますか？

UART：

9. USB-シリアルブリッジコントローラーが接続されている他のUARTデバイス（またはラインドライバー）の電源は、VDDD（またはVCCIO）と同じか、それと同等なものですか？

10. USBシリアルブリッジコントローラーのすべてのUARTラインは、外部コンポーネントを使用せずに他のUARTデバイス（またはラインドライバー）に直接接続されていますか？

SPI（CY7C65211 / 211A / 215 / 215Aのみ）

11. USBシリアルブリッジコントローラーが接続されている他のSPIデバイス（マスター/スレーブ）の電源はVDDDと同じか、それと同等なものですか？

12. SSEL（slave select n）ラインに10kΩプルアップ抵抗が接続されていますか？

13. MISO、MOSI、およびSCLKラインは、別のSPIデバイスに直接接続されていますか？

I2C（CY7C65211 / 211A / 215 / 215Aのみ）

14. USBシリアルブリッジコントローラーが接続されている他のI2Cデバイスの電源はVDDDと同じか、それと同等なものですか？

15. I2Cラインは外部プルアップ抵抗を使用してVDDDにプルアップされていますか？

SCLおよびSDAラインのプルアップ抵抗の推奨値は、100 kHz動作周波数の場合は4.7kΩ、400 kHz動作周波数の場合は2.2kΩです。

JTAG（CY7C65211 / 211A / 215 / 215Aのみ）

16. USB-シリアルブリッジコントローラーが接続されている他のJTAGデバイス（JTAGスレーブ）の電源はVDDDと同じか、それと同等なものですか？

17. USBシリアルブリッジコントローラーのすべてのJTAGラインは、外部コンポーネントを使用せずに他のJTAGスレーブデバイスに直接接続されていますか？

表2に、USBシリアルブリッジコントローラーICと、対応するリファレンスデザインキット（RDK）/開発キット（DVK）の詳細を示します。例については、それぞれのUSBシリアルブリッジコントローラーのキットの回路図をご参照願います。

Note： USBシリアルブリッジコントローラーIC（「非A」パーツ）：CY7C65211、CY7C65213、CY7C65215は、対応する「A」パーツ：CY7C65211A、CY7C65213A、およびCY7C65215Aとピン互換であり、開発とテストの目的でそれぞれのDVKで置き換えることができます。

表2. USB-シリアルブリッジコントローラーDVK/RDK

Version: **

Translation - Japanese: USB-シリアル：ハードウェア設計の回路図のチェックリスト - KBA231249 - Community Translated (JA)

Question:
What are the items that I need to verify while designing a schematic for successful operation of USB-Serial Bridge Controllers?

Answer:
Following is the list of critical items that you need to follow while designing a schematic design for USB-Serial Bridge Controllers.

1. Are all power pins VCC (or VBUS) and VCCIO (or VDDD) powered to a proper voltage level in accordance with Table 1?

2. If 1.71 V £ VDDD/VCCIO £ 1.89 V, is VCCD shorted to VDDD/VCCIO?

If VDDD/VCCIO > 2 V, is a 1-uF decoupling capacitor connected to the VCCD/VCCIO pin?

3. Is ferrite bead L1 connected at the VBUS pin of the USB connector?

Ferrite beads should be connected at the USB connector to isolate the noise from the USB Host. See the respective USB-Serial controller DVK/RDK schematics (CYUSBS232 RDK, CYUSBS234 DVK, CYUSBS236 DVK).

4. Is a 0.1-uF decoupling capacitor connected to the VBUS/VCC pin of the USB-Serial device close to the IC?

5. Are the decoupling capacitors, 0.1 uF and 4.7 uF, connected to the VCCIO/VDDD pin of the USB-Serial device close to the IC?

This will remove the low and high frequency noise.

6. USB-Serial Bridge Controllers have a built-in ESD protection of 2.2 kV. For protection over 2.2 kV, have you connected the ESD diodes to the VBUS/VCC, USBDP, and USBDM lines?

7. Is the Reset (XRES) pin pulled high externally using a resistor?

The USB-Serial devices support an Active Low external reset. The XRES pin should be held low for a minimum of 1 us to reset the USB-Serial controller.

The nXRES pin can be tied to VDDD (or VCCIO) through an external resistor and to ground (GND) through an external capacitor (minimum 1-µs time constant), as shown in Figure 1. To meet the 1-µs pulse width requirement, the recommended values for R and C are 100 Ω and 0.01 µF, respectively.

Figure 1. Example Reset Circuit for USB-Serial Bridge Controller

GPIO:

8. Are all input pins pulled high (or low) using a 10-kΩ pull-up (or pull-down) resistor?

UART:

9. Is the power supply of the other UART device (or line driver) to which the USB-Serial Bridge Controller is connected the same as or equal to VDDD (or VCCIO)?

10. Are all UART lines of the USB-Serial Bridge Controller directly connected to the other UART device (or line driver) without the use of any external components?

SPI (only for CY7C65211/211A/215/215A)

11. Is the power supply of the other SPI device (master/slave) to which the USB-Serial Bridge Controller is connected the same as or equal to VDDD?

12. Is a 10-kΩ pull-up resistor connected on the SSEL (slave select n) line?

13. Are the MISO, MOSI, and SCLK lines connected directly to another SPI device?

I2C (only for CY7C65211/211A/215/215A)

14. Is the power supply of the other I2C device to which the USB-Serial Bridge Controller is connected the same as or equal to VDDD?

15. Are the I2C lines pulled up to VDDD using external pull-up resistors?

The recommended values for pull-up resistors on the SCL and SDA lines are 4.7 kΩ for the 100-kHz operating frequency and 2.2 kΩ for the 400-kHz operating frequency.

JTAG (only for CY7C65211/211A/215/215A)

16. Is the power supply of the other JTAG device (JTAG slave) to which the USB-Serial Bridge Controller is connected the same as or equal to VDDD?

17. Are all JTAG lines of the USB-Serial Bridge Controller directly connected to the other JTAG slave device without the use of any external components?

Table 2 lists the USB-Serial Bridge controller ICs and the details of the corresponding Reference Design Kit (RDK)/ Development Kit (DVK). For examples, see the Kit schematic of the respective USB-Serial Bridge Controllers.

Note: The USB-Serial Bridge controller ICs (‘non-A’ parts): CY7C65211, CY7C65213, are CY7C65215 are pin-compatible with their corresponding ‘A’ parts: CY7C65211A, CY7C65213A, and CY7C65215A, and can be replaced in their respective DVK for development and testing purposes.

Table 2. USB-Serial Bridge Controllers DVK/RDK

Community Translated by keni_4440091          Version: **

Translation - English: Rsense Design Considerations On CCG3PA Applications – KBA229013

接地センスを有効にするために下記を確認して下さい。

1. 電流センス抵抗のポジティブ側に測定したグランドピンを配線して下さい。電流センス抵抗のネガティブ側にCCG3PAのCSPとGNDピンを配線して下さい。
2. 外部部品に対するGNDリファレンスとしてType-C GNDラインを使用して下さい。
3. 電流測定範囲によれば、Rsenseは5mオームまたは10mオームになります。Rsenseの推奨値は5mオームです。
4. Rsenseを配線するにはケルビンセンスラインを使用して下さい。センスラインはセンス抵抗端子に直接接続する必要があります；　トレースは対称に、同じ長さになるようにし、できるだけ短く、太くする必要があります（トレースインピーダンスはできる限り低くするようにして下さい）。　　
5. ノイズを除去するためにRsenseの反対側にバイパスコンデンサを配置して下さい。