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Version: **A P-channel MOSFET is used as the VBUS provider control FET in CCG3PA designs (CYPD3171, CYPD3174, CYPD3175, CYPD3195, and CYPD3196 parts)....
A P-channel MOSFET is used as the VBUS provider control FET in CCG3PA designs (CYPD3171, CYPD3174, CYPD3175, CYPD3195, and CYPD3196 parts). Consider the following when selecting a suitable P-MOSFET:
1. Drain-source breakdown voltage (VDS)
Make sure that the VDS breakdown voltage is at least 10% higher than the maximum VBUS_IN voltage in the application design. For Power Delivery (PD) designs supporting a VBUS voltage up to 20V, an FET with the VDS breakdown voltage of 25 V or more is recommended.
2. On-state drain current (ID)
Ensure that the rated on-state drain current (ID) is higher than the maximum VBUS current in your application. ID should be greater than 5 A for a PD design which supports the maximum VBUS current of 5 A.
3. Drain-source on-state resistance (RDS(ON))
Drain-source resistance of the MOSFET must be as low as possible. RDS(ON) of <10 mΩ at 5 V VGS is preferable. For designs with PPS support, it is critical to have low voltage drop across the FET, and thus lowest RDS(ON) at around 3.2V VGS.
4. Gate plateau voltage (VGP)
In most power MOSFET datasheets, VGS(th) is specified at ID of 250µA. The gate plateau voltage (VGP) can be used to determine the gate- source voltage at which the MOSFET is fully enhanced (i.e., turned on).VGP for the maximum rated ID is mentioned explicitly in the FET datasheet or can be found using a plot of VGS vs the Total Gate Charge. VGP of the FET must be less than 2.8 V. This will enable the FET to be completely turned on under 3.2V VGS.
See the following example VBUS provider FET circuit for other considerations while designing the FET circuitry:
Figure 1. VBUS Provider FET circuit
CCG3PA drives the VBUS_P_CTRL pin to 0 V when the FET is turned ON. You should ensure that the absolute maximum rating of VGS is more than the maximum VBUS_IN voltage. If this condition is not satisfied, a Zener diode (D11) with the Zener voltage less than the absolute maximum VGS can be used as shown in figure to clip the gate to the source voltage within the FET rating. Diode (D11) is not required if the FET can handle VGS greater than VBUS_IN.
Resistor (R43) is added to limit the current through the Zener diode to a safe level.
The ratio of R5 and R43 must be as high as possible. This will ensure a higher VGS at relatively low values of the VBUS voltage.