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Question: For Hybrid Sector architecture in Cypress Flash, is there one PPB bit for each 4-KB Sector or is there a single PPB bit for all the 4-KB Sectors combined?
Answer: There is a separate PPB bit for each 4-KB sector when hybrid sector architecture is configured in Cypress flash devices.
For example, the sector address map for S25FS512S (bottom 4-KB sector) device is shown below (see the datasheet).
SA0 – SA7
Eight 4-KB sectors that should use a parameter 4-KB sector erase command (P4E, 4P4E)
224-KB sector that should use a sector erase command (SE, 4SE)
SA9 – SA263
256-KB sector that should use a sector erase command (SE, 4SE)
When the flash device is configured with hybrid sector architecture, each 4-KB sector and 224-KB sector can be protected or unprotected by individual PPB bits. The corresponding PPB bit is decided by the sector address. When the flash device is configured at uniform sector architecture, the eight 4-KB sectors and one 224-KB sector are combined as one 256-KB sector. One single PPB bit takes the control on the entire combined 256-KB sector.
Version: **Question: When using the Write Register command (WRR 01h), programming the Configuration Register-1 from 0x00 to 0x20 is successful, but wh...
Question: When using the Write Register command (WRR 01h), programming the Configuration Register-1 from 0x00 to 0x20 is successful, but when programming from 0x20 back to 0x00, programming is unsuccessful and the Status Register-1, Bit-6 (SR1) is set to “1” (programming error occurred). What may be causing the problem?
Answer: The issue is that when programming, the value 0x20 to Configuration Register-1, Bit 5 (CR1) is One-Time Programmable (OTP). Therefore, any attempt to change CR1 back to “0” will fail and the Status Register-1, Bit 6 (P_ERR in SR1) will be set to “1” indicating the occurrence of a programming error. The same error is expected for Configuration Register-1, Bits 4, 3, and 2 (CR1[4:2]). When set to “1”, the Programming Error bit can be reset to “0” with the Clear Status Register (CLSR 30h) command.
There is no provision to support either QPI or QSPI modes of operation.The Semper™S28HS-T and S28HL-T series is a memory device with an octal interface that supports both Octal (x8) Peripheral Interface (OPI), as well as legacy Serial (x1) Peripheral Interface (SPI). However, the default data bus width setting from the factory is Serial (x1) mode. Configuration Register-5, bit-0 (CFR5x) is user-defined, in either SPI (x1) mode or OPI (x8) data bus width. SPI (x1) mode supports SDR (1S-1S-1S) only; OPI (x8) mode supports both SDR (8S-8S-8S) and DDR (8D-8D-8D). Therefore, QPI (4-4-4) and QSPI (1-4-4) modes are not supported.
See the following sections in the S28HS-T/S28HL-T datasheet:
- “Transaction Protocol” for SPI and Octal protocol definitions
- “Configuration Register 5 - CFR5x” for selection of either SPI (x1) or Octal (x8) modes
- “Transaction Table” for specific SPI and Octal transition functions, names, and commands