Version: **

Sectors are the erase units of a flash memory. Infineon serial NOR flash devices offer a flexible sector architecture with two options:

• Uniform sector: The entire flash array is divided into equally sized uniform sectors
• Hybrid sector size: Physical set of 4-KB sectors present at the top or bottom of the address space

Whether a device supports hybrid sector architecture or not can be determined through the model number in the ordering part number (OPN) of the device or the configuration register settings. See the respective device datasheet for detailed OPN definition including model number information.

Configuration register settings can be modified to change the default sector architecture. For example, in the FS-S device family, one particular bit of the configuration register (CR3NV [3]) enables or disables the 4-KB parameter sectors. The default state of CR3NV[3] bit is 0, which means 4-KB sectors are enabled. The configuration register can be programmed to set the CR3NV[3] bit to 1 to disable 4-KB parameter sector overlay and choose the uniform sector size option. The CR3NV[3] bit is an OTP (one time programmable) bit, which means it can be programmed only once in the entire lifecycle of the flash memory.

4-KB parameter sectors can be at the bottom or top of the flash device. Their location can be changed by modifying the TBPARM bit of the configuration register. TBPARM is also an OTP bit. For example, the default value of the TBPARM bit is 0, indicating that the 4-KB physical sectors are located at the bottom (low address). Programming the configuration register to set TBPARM bit to ‘1’ will change the location of the parameter sectors to top (high address) space.

There are special commands to perform sector erase operation on these 4-KB parameter sectors. The P4E (20h) and the 4P4E (21h) commands can be used to erase parameter sectors. The P4E command can take 3-byte as well as 4-bytes address, whereas the 4P4E command always expects 4-bytes address. The P4E and 4P4E commands are ignored when the device is configured for uniform sector size option.

Examples:
Sector organization in FL-S and FS-S devices –

• S25FL128S/S25FL256S
  • Uniform sector: The entire flash is divided into uniform 256-KB sectors
  • Hybrid sector size: Physical set of thirty-two 4-KB sectors present at the top or bottom of the address space; all remaining sectors of 64-KB size.
• S25FS512S
  • Uniform sector: The entire flash is divided into uniform 256-KB sectors
  • Hybrid sector size: Physical set of eight 4-KB sectors and one 224-KB sector present at the top or bottom of the address space; all remaining sectors are of 256-KB size.

In FL-S device, the 64-KB sector erase command (D8h or DCh) can also be used to erase a group of sixteen 4-KB parameter sectors. The advanced sector protection feature provides a PPB and a DYB protection bit for each of these thirty-two 4-KB parameter sectors. If the 64-KB sector erase command is applied to a certain 64-KB range such that it includes a protected 4-KB sector, the erase operation will not be executed on the protected range of memory and the E_ERR bit in the status register will be set.

On the other hand, in the FS-S family, only the parameter sector erase commands (20h or 21h) must be used to erase 4-KB sectors individually. The uniform sector erase command (D8h or DCh) should be used to erase all remaining sectors (224-KB sector and 256-KB sectors). The same conditions are applicable for 128Mb/256Mb FS-S device parameter sector and uniform sectors (32-KB sector and 64-KB sectors) as well.

Version: **

Question:
How can a portion of the main memory array (256Mb) of S25FS512S be protected and used as ‘read-only’?

 Answer:
A combination of the Status Register-1 nonvolatile bits BP2, BP1, BP0 (SR1NV[4:2]), and the Configuration Register-1 Nonvolatile Bit 5 CR1NV[5] (TBPROT_O) bit can be used to protect an address range of the main memory array from program and erase operations. The size of the range is determined by the value of the BP bits and the upper or lower starting point of the range is selected by the TBPROT_O bit.  To illustrate the implementation of a protection scheme on a portion of the main memory array, protecting the lower portion (256 Mb) of the main memory array will be used as the example. 

Status Register-1 Nonvolatile bits SR1NV[4:2] (BP_NV2, BP_NV1, BP_NV0):
These bits define the main flash array area to be software-protected against program and erase operations. BP bits allow you to optionally protect a portion of the memory array, ranging from 1/64, 1/32, 1/16, and so on, up to the entire memory array. When one or more of the BP bits is set to 1, the relevant memory area is protected from program and erase operations. Following are the settings to protect the lower portion of the main memory array (256 Mb):

• BP_NV2 = 1
• BP_NV1 = 1
• BP_NV0 = 0

Note:  It is important to note that CR1NV[3] (BPNV_O) remains set at “0” (default nonvolatile).  

Table 1. Status Register 1 Nonvolatile (SR1NV)

CR1NV[3] (BPNV_O): The BP bits are selected as either volatile or nonvolatile, depending on the state of the BP nonvolatile bit (BPNV_O) in the configuration register CR1NV[3].  When CR1NV[3]=0, the nonvolatile version of the BP bits (SR1NV[4:2]), is used to control Block Protection and the Write Register (WRR) command writes SR1NV[4:2] and updates SR1V[4:2] with the same value. When CR1NV[3]=1, the volatile version of the BP bits (SR1V[4:2]), is used to control Block Protection and the WRR command writes SR1V[4:2] and does not affect SR1NV[4:2].  The CR1NV[3] bit (BPNV_O) should remain in the default state, set as “0” = nonvolatile.  Keeping CR1NV[3] set as default “0” = nonvolatile, during Power-On Reset (POR), hardware reset, or software reset, the bit values in SR1NV[4:2] will be copied to SR1V[4:2], as the default value for the SR1V[4:2] volatile bits.  If CR1NV[3] is set at “1” = volatile, SR1V[4:2] volatile (BP 2-0) bits will be set to binary 111 after Power-on-Reset (POR), hardware reset, or software reset. See Table 2 and Table 3.

CR1NV[5] (TBPROT_O): When TBPROT_O is set to a “0” (default value when shipped from Infineon), the Block Protection is defined to start from the top (maximum address) of the array. When TBPROT_O is set to a “1”, the Block Protection is defined to start from the bottom (zero address) of the array. The desired state of TBPROT_O must be selected during the initial configuration of the device during system manufacture; before the first program or erase operation on the main flash array. CR1NV[5] (TBPROT_O) must not be programmed after programming or erasing is done in the main flash array.

Table 2. Configuration Register 1 Nonvolatile (CR1NV)

Table 3. Lower Array Start of Protection (TBPROT_O = 1)

Summary

With the combination of the Status Register-1 nonvolatile bits BP2, BP1, BP0 (SR1NV[4:2]) and the Configuration Register-1 nonvolatile Bit 5 CR1NV[5] (TBPROT_O) an address range within the main memory array will be protected from program and erase operations.  However, the desired state of TBPROT_O must be selected during the initial configuration of the device during system manufacture, before the first program or erase operation on the main flash array.  CR1NV[5] (TBPROT_O) must not be programmed after programming or erasing is done in the main flash array.  With regards to the CR1NV[3] bit (BPNV_O), it should remain in the default state, set as “0” (nonvolatile), as during POR, hardware reset, or software reset, the bit values in SR1NV[4:2] will be copied, as the default bit values for SR1V[4:2] volatile bits. 

For more details, see the S25FS512S Datasheet.

Community translated by :  Kenshow

AN226576 は、サイプレスの最新の高密度、高性能メモリを使用して設計するために必要な重要な概念の概要を説
明し、システムで HyperRAM を使用する主な利点と一般的な使用例のシナリオをリストアップします。このアプ
リケーションノートは、市場をリードする SoC と同様なサイプレスの Traveo™ MCU を使用した HyperRAM を設
計するためのリソースを提供します。

Japanese Translation: https://community.cypress.com/t5/Knowledge-Base-Articles/%E3%82%B5%E3%82%A4%E3%83%97%E3%83%AC%E3%82%B9%E3%83%95%E3%83%A9%E3%83%83%E3%82%B7%E3%83%A5%E8%A3%BD%E5%93%81%E3%81%AE%E3%83%8F%E3%82%A4%E3%83%96%E3%83%AA%E3%83%83%E3%83%89%E3%82%BB%E3%82%AF%E3%82%BF%E3%83%BC%E3%81%AB%E3%81%8A%E3%81%91%E3%82%8B%E6%B0%B8%E7%B6%9A%E7%9A%84%E4%BF%9D%E8%AD%B7%E6%A9%9F%E6%A7%8B-KBA232295-Community/ta-p/269575

Author: ApurvaS_36           Version: **

Question:
For Hybrid Sector architecture in Cypress Flash, is there one PPB bit for each 4-KB Sector or is there a single PPB bit for all the 4-KB Sectors combined?

Answer:
There is a separate PPB bit for each 4-KB sector when hybrid sector architecture is configured in Cypress flash devices.

For example, the sector address map for S25FS512S (bottom 4-KB sector) device is shown below (see the datasheet).

When the flash device is configured with hybrid sector architecture, each 4-KB sector and 224-KB sector can be protected or unprotected by individual PPB bits. The corresponding PPB bit is decided by the sector address. When the flash device is configured at uniform sector architecture, the eight 4-KB sectors and one 224-KB sector are combined as one 256-KB sector. One single PPB bit takes the control on the entire combined 256-KB sector.

You should set the required sector architecture first, before performing any other operation on the flash including sector protection. The following application note AN98551 - Advanced Sector Protection (ASP) in Cypress Quad SPI, Octal SPI, and HyperFlash Device Families

can be referred to learn about sector protection techniques in Cypress flash devices.