Strictly necessary cookies are on by default and cannot be turned off. Functional, Performance and Tracking/targeting/sharing cookies can be turned on below based on your preferences (this banner will remain available for you to accept cookies). You may change your cookie settings by deleting cookies from your browser. Then this banner will appear again. You can learn more details about cookies HERE.
Strictly necessary (always on)
Functional, Performance and Tracking/targeting/sharing (default off)
The PSoC™ programmer command-line interface (PPCLI) tool in the PSoC™ programmer installation directory (C:\Program Files (x86)\Cypress\P...
The PSoC™ programmer command-line interface (PPCLI) tool in the PSoC™ programmer installation directory (C:\Program Files (x86)\Cypress\Programmer\ is the default) provides CLI access to all features of the PSoC™ programmer tool. The tool can be run in a command prompt instance or through a script which provides a means of automating the programming of your devices. See the PSoC™ programmer command-line interface guide for details.
The PPCLI tool can be used in the following ways:
Running the PPCLI tool by passing a script file
Executing the PPCLI tool
Executing the PPCLI tool using the command prompt
These options are described in the following sections.
1. Running the PPCLI tool by passing a script file
You can pass a script file in .cli format to ppcli.exe using the --runfile command line option as shown in Figure 1.
Run the script using the following command: ppcli.exe “--runfile <path_to_script>” Ensure that the <path_to_script> uses forward slash (/) and does not have space or special characters.
Figure 1. Passing a script file to ppcli.exe
Figure 2. Example script file
1.1 Creating the script file
An example .cli script for PSoC™ 4 and PSoC™ 3/5LP MCUs is attached with this document. The script can be used to program the hex file for a sample application (Blinky LED project for CY8CKIT-043 kit (PSoC™ 4 MCU) and CY8CKIT-059 kit (PSoC™ 5LP MCU)).
The following tables provide the details of commands used in the example script:
Table 1. Initial configuration and device acquire process (common for PSoC™ 3, PSoC™, 5LP, and PSoC™ 4 MCUs)
PSoC™ 3 MCU, PSoC™ 4 MCU, PSoC™ 5LP MCU, and some of PSoC™ 6 MCU devices have a powerful and flexible programmable digital perip...
PSoC™ 3 MCU, PSoC™ 4 MCU, PSoC™ 5LP MCU, and some of PSoC™ 6 MCU devices have a powerful and flexible programmable digital peripheral system. In addition to a set of fixed function blocks they have universal digital blocks (UDBs) and an extensive signal routing system called the digital system interconnect (DSI).
While using the PSoC™ Creator to create custom designs the "Asynchronous path(s) exist" warning may occur when building the project. This happens when there is a timing difference between the clocking network and the DSI. For example, in the case of fixed function block and UDB interface connection as shown in Figure 1 you might end up getting this warning.
Figure 1: Asynchronous paths between fixed function block and UDB interface
For Example, in the Figure 1, a fixed-function Component (Timer_1) and a UDB Component (Counter_1) share a common clock. The Counter_1 Component requires the count input to be synchronous with the clock input. However, the cc output from the Timer_1 Component may not be synchronous with the input clock (clock_1) resulting in this warning.
This warning can be resolved by adding a Sync component as shown in Figure 2. When you need to use a signal from one clock domain in another clock domain, you can use the Sync component to line up that signal’s transitions to the clock domain of the destination. In this case, the Sync component is clocked using the same clock as the destination; the Sync component ensures that the count input is synchronized with Clock_1.
Figure 2: Adding the Sync Component
See the static timing analysis (STA) report for more information on the timing violation. The STA report is available under the Results tab of the Workspace Explorer.
Figure 3: Viewing the STA report
Figure 4: Timing violation section of the STA report
When building a PSoC Creator project that uses UDBs, you may get the error “Unable to pack the design into available UDBs”. This error oc...
When building a PSoC Creator project that uses UDBs, you may get the error “Unable to pack the design into available UDBs”. This error occurs when the synthesis tool cannot route and place all UDBs used in the design. To view the current UDB resource utilization, click the Resource Meter tab on the left of the PSoC Creator window, as seen in the image below.
Figure 1: Resource Meter Tab
This error may occur even when the UDB resources have not been utilized completely. As seen in Figure 1, the error is observed when the UDB resource utilization is only 76 percent. To understand this, it is necessary to understand the UDB architecture and routing and placement tool. The router and placement algorithms are never 100 percent efficient to use up all areas.
A UDB consists of two “12C4” programmable logic devices (PLD). A PLD has 12 inputs, which feed across eight product terms (PT) in the AND array. In a given product term, the true (T) or complement (C) of the input can be selected. The output of the PTs are inputs into the OR array.
Figure 2: PLD 12C4 Structure from TRM
The system should be designed such that it uses the resources optimally. The PLD architecture contains PTs; if a particular output uses more number of inputs to the block and corresponding PTs, then other macrocells and PTs may not be used in this PLD. This is because the tool is not able to find routes for all of the logic, due to the densely packed design. If the placer cannot find a complete block for the logic under consideration it may use a new PLD. For example, it is inefficient to use all the inputs for a particular PLD to generate only one output. This would mean the remaining AND, OR gates are unused when generating one out of four possible outputs from the macrocell (MC). Thus, a high number of inputs and a low number of outputs increases this inefficiency.
To understand the detailed PLD placement summary view the report file associated with a project. The report file is present in the Results tab of the Workspace Explorer as shown in the image below.
Figure 3: Viewing the project.rpt File
The report file contains details regarding the number of PLDs used in a project and the average input, product terms, and macrocells used per PLD.
Figure 4: PLD Packing Summary
It also contains a digital placement section, which shows the blocks/instances that could not be placed. You can see the inputs and outputs in each PLD to have a better understanding.
Figure 5: Digital Placement Section
Here are some possible solutions to resolve this issue:
Use fixed-function blocks in your design. If possible, replace some UDB components with fixed-function blocks.
Identify the cause of the issue by removing and adding back blocks.
Analyze the component placement and force the placement to a cell. If you have a known working placement, you may be able to use it by adding a control file to the TopDesign component. To add the control file, right-click on the Top-Design component in the Components tab and click Add Component Item > Control File. Use the -.fftgenctrlfile argument in Build Settings > Fitter to export a control file after successful placement in codegentemp/cyp3fit_results.ctl.
For more details about adding a control file to your project, refer to the following documents: