Author: ShusakuS_56           Version: **

Question:

I want to know the execution time of some software. Is there a method to measure the execution time without using a debugger?

Answer:

You can measure the approximate software execution time using the hardware timer (TCPWM). Here is the code snippet for "Hello World".

Code 1. Original “Hello World”

To measure software execution time, make the following modifications to the “Hello World” code:

1. Add the TCPWM timer start command and the TCPWM timer stop command before and after printf ("Hello World"); to the ”.

Code 2. Adding TCPWM Timer Start and Timer Stop Commands

2. Then, add a command to read the timer value of the corresponding TCPWM. This timer value counts the number of clocks. Therefore, the software execution time can be calculated as:

     [Example] Clock Frequency = 20 MHz, Value of TimerCount = 0xF000 (0d61440)

To make the measurement time more accurate, take the following measures.

1. Increase clock speed.
2. Measure the time from starting the counter to stopping it. Then, subtract from the count value. Here is an example:

Note: This KBA applies to the following series of Traveo II MCUs:

• CYT2B Series
• CYT4B Series
• CYT4D Series

Author: ShusakuS_56           Version: **

Question:

Why doesn't the counter start when I enable the counter in TCPWM?

Answer:

If the counter does not start, make sure that the following are set correctly:

(1) CLK Setting

(2) Hardware control signals

(1) CLK Setting

TCPWM has a system clock and a counter clock.

The system clock is supplied from CLK_PERI via a divider. This clock is used for trigger synchronization.

The counter clock is supplied from CLK_PERI via Peripheral Clock Dividers. This clock is used for counter control. You should set the clock for each counter.

The number of these clocks differs for the CYT2B/CYT4B/CYT4D series. For more details, see the "Clock Diagram" section in the corresponding datasheet.

(2) Hardware control signals

Even if the counter is enabled, the counter does not start unless the counter's hardware control signals (Reload, Start, Stop, Count, Capture0, Capture1) are enabled. The counter's hardware control signals must be selected from the following Trigger Input signal using the “TCPWMx_GRPy_CNTz_TR_IN_SEL0” and “TCPWMx_GRPy_CNTz_TR_IN_SEL1” register.

- Fixed at ‘0’ or ‘1’

- Connect signals from the output of other peripherals or external terminals via the Trigger Multiplexer block.

[Example]

In timer mode, hardware control signals are used as follows:

- Reload         : Active "H". Initializes and starts the counter.

When "H" is supplied, the counter starts from the initial value (Up mode: 0, Down mode: period).

If neither Reload nor Start is supplied, the counter will not start.

- Start             : Active "H". Starts the counter.

When "H" is supplied, the counter starts from the current counter value.

If neither Reload nor Start is supplied, the counter will not start.

- Stop             : Active "H". Stops the counter.

When "H" is supplied, the counter does not start.

- Count          : Active "H". Count event increments/decrements the counter.

When "L" is supplied, the counter does not start.

- Capture0     : Not used.

- Capture1     : Not used.

These signals can also be generated by with the TCPWMx_GRPy_CNTz_TR_CMD register.

For more details, see the "Timer, Counter, and PWM" section in the corresponding Technical Reference Manual.

Note: This KBA applies to the following series of Traveo II MCUs:

• CYT2B Series
• CYT4B Series
• CYT4D Series

TCPWM Interrupt Does Not Occur in Traveo II Fam... | Cypress Developer Community

Author: ShusakuS_56           Version: **

Question:

I am generating an interrupt to the CPU with the TCPWM Counter Overflow (OV) event. However, when the reload signal is input to the counter, no interrupt occurs. How do I generate an interrupt when a reload signal is input to the counter?

Answer:

When a reload signal is input to the TCPWM counter, overflow of the counter occurs, but no TC event occurs. This is as specified.

If you want to generate an interrupt even when a reload signal is input to the counter, use a compare match to generate an interrupt.

For example, set the compare value to "0" in the "TCPWMx_GRPy_CNTz_CC0" register and enable CC0_MATCH in the “TCPWMx_GRPy_CNTz_INTR” register. When the counter is set to "0" by the reload signal, it matches the compare value. Therefore, a compare match interrupt is generated as shown below. ('x' signifies the TCPWM instance number, 'y' is the group number and 'z' is the counter in the respective TCPWM group.)

Note that Interrupts are counter mode specific and can be generated for a Terminal Count (TC) or Compare/Capture0/1 (CC0/1) event.

For more details, see the "Timer, Counter, and PWM" section in the corresponding the Technical Reference Manual:

Note: This KBA applies to the following series of Traveo II MCUs:

• CYT2B Series
• CYT4B Series
• CYT4D Series

Author: ShusakuS_56           Version: **

Question:

In Traveo™ family, if a new A/D conversion is started before the previous A/D conversion result is read, the next conversion will start; however, the result will not be saved. Can this feature be used in Traveo II Family?

Answer:

No. This feature is different for Traveo and Traveo II. In Traveo II, new results are overwritten.

For more details, see the "SAR ADC" section in the corresponding the Architecture Technical Reference Manual:

Note: This knowledge base article applies to the following series of Traveo II MCUs:

• CYT2B Series
• CYT4B Series
• CYT4D Series

Author: ShusakuS_56           Version: **

Question:

Can the Arm^® Cortex^®-M4/M7 and Cortex-M0+ cores in Traveo™ II family be debugged from the same JTAG?

Answer:

Yes. Both cores can be debugged from the same JTAG. For details of the debugger, contact the following third parties:

• Green Hills Software Ltd: https://www.ghs.com/
• IAR Systems AB: https://www.iar.com/iar-embedded-workbench/partners/cypress/
• Lauterbach GmbH: https://www.lauterbach.com/frames.html?home.html
• iSYSTEM AG: https://www.isystem.com/

Note: This KBA applies to the following series of Traveo II MCUs:

• CYT2B Series
• CYT4B Series
• CYT4D Series

Author: ShusakuS_56           Version: **

Question:

Traveo™ II has a Cortex-M0+ core in addition to the Cortex-M4/M7 core. To reduce the load on the Cortex-M4/M7 core, I want the Cortex-M0+ core to process some of the load. Is that possible?

Answer:

Yes. It is possible. However, the Cortex-M0+ core is basically used for security processing. Please verify the security processing on your system.

Note: This KBA applies to the following series of Traveo II MCUs:

- CYT2B Series

- CYT4B Series

- CYT4D Series