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Question:
What is the difference between the "Load Volatile Configuration Register" command and the "Read Volatile Configuration Register" command in HyperFlash?

Answer:
In HyperFlash, the Load Volatile Configuration Register command is used to update the contents in Volatile Configuration Register (VCR), whereas the Read Volatile Configuration Register command is used to read out the VCR contents.

HyperFlash contains two copies of the Configuration Register: Nonvolatile Configuration Register (NVCR) and Volatile Configuration Register (VCR).

The HyperFlash device uses the contents of the NVCR to define bus characteristics upon power-up or after a Hardware Reset. If the host system loads the VCR (by sending Load Volatile Configuration Register command), the configuration in VCR will take effect. Once the VCR is loaded, only a power-up or Hard Reset will reload the NVCR settings to take effect. However, if the NVCR settings are needed without a power-up or Hard Reset, the Load Volatile Configuration Register command can be used to update VCR settings to the same value as NVCR. The NVCR is intended to hold a default setting to align with the host controller settings during boot operation. The VCR is often updated with optimized settings during/after the boot process, or for setting temporary configuration values.

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Question:
Infineon has the latest 45-nm SEMPER NOR flash with HyperBus interface (S26HL-T and S26HS-T series), which can support legacy SPI (x1) mode and HyperBus (x8) mode. Can I use it like a normal SPI (x1) NOR flash?

Answer:
SEMPER NOR flash with HyperBus interface (S26HL-T and S26HS-T series) has some ordering part numbers (OPN) that work in legacy SPI (x1) mode by factory default.

When SEMPER NOR flash with HyperBus interface works in legacy SPI (x1) mode, the Read Device ID (RDIDN_0_0, 9Fh) command will output the 8-bit byte stream from flash. Since the Device ID is aligned in 16-bit length (“word” type), the Device ID byte value is in the lower 8-bit; the upper 8-bit is padded with the “00h” value.

For example, if we read Device ID from S26HL512T in legacy SPI (x1) mode, the output byte stream will be: 0x34 – 0x00 – 0xA6 – 0x00 – 0x1A – 0x00 – 0xA2 – 0x00 …

Therefore, when using the code to read and pair the Device ID developed for SPI/QSPI flash, consider the Device ID pattern in byte mode and handle the “00h” padding correctly for every 16-bit width.

More information is available in the “Device ID Address Space” section in the datasheet:

Figure 1. S26HL-T/S26HS-T Device ID Datasheet Table

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Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. By issuing the DYB Write command, a DYB is cleared to ‘0’ or set to ‘1’, thus placing each sector in the protected or unprotected state respectively. This feature allows software to easily protect sectors against inadvertent changes, yet does not prevent the easy removal of protection when changes are needed. The DYBs can be set or cleared as often as needed as they are volatile bits.

Every sector in the main flash array has an associated volatile dynamic protection bit (DYB). When the bit is ‘0’, the sector is protected from program and erase operations. When the bit is ‘1’, the sector is in unprotected state. This bit is written to and read from the flash in the form of a one-byte data, which is held in DYB Access Register (DYBAR).

If the DYBAR value associated with a particular sector is 0x00, the particular sector is protected from program and erase operations by DYB. If the DYBAR value associated with a particular sector is 0xFF, the particular sector is not protected from program and erase operations by DYB.

Table 1. DYB Access Register (DYBAR)

The DYBAR value can be read using the DYB Read (0xE0) command. The DYBAR value can be written using the DYB Write (0xE1) command.

Please note that the protection scheme only protects the sector against program and erase; read operations are not impacted.

The dynamic sector protection scheme can be executed in the following way:

1. Drive CS# LOW.
2. Send the WREN command.
3. Drive CS# HIGH.
4. Drive CS# LOW.
5. Send the DYBWR command.
6. Send the 32-bit address selecting location zero within the desired sector.
7. Send the data byte (00h for protecting, FFh for unprotecting).
8. Drive CS# HIGH.

DYBAR is a volatile register; it is reset to the default value after a power cycle or reset.

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Question:
How can a portion of the main memory array (256Mb) of S25FS512S be protected and used as ‘read-only’?

 Answer:
A combination of the Status Register-1 nonvolatile bits BP2, BP1, BP0 (SR1NV[4:2]), and the Configuration Register-1 Nonvolatile Bit 5 CR1NV[5] (TBPROT_O) bit can be used to protect an address range of the main memory array from program and erase operations. The size of the range is determined by the value of the BP bits and the upper or lower starting point of the range is selected by the TBPROT_O bit.  To illustrate the implementation of a protection scheme on a portion of the main memory array, protecting the lower portion (256 Mb) of the main memory array will be used as the example. 

Status Register-1 Nonvolatile bits SR1NV[4:2] (BP_NV2, BP_NV1, BP_NV0):
These bits define the main flash array area to be software-protected against program and erase operations. BP bits allow you to optionally protect a portion of the memory array, ranging from 1/64, 1/32, 1/16, and so on, up to the entire memory array. When one or more of the BP bits is set to 1, the relevant memory area is protected from program and erase operations. Following are the settings to protect the lower portion of the main memory array (256 Mb):

• BP_NV2 = 1
• BP_NV1 = 1
• BP_NV0 = 0

Note:  It is important to note that CR1NV[3] (BPNV_O) remains set at “0” (default nonvolatile).  

Table 1. Status Register 1 Nonvolatile (SR1NV)

CR1NV[3] (BPNV_O): The BP bits are selected as either volatile or nonvolatile, depending on the state of the BP nonvolatile bit (BPNV_O) in the configuration register CR1NV[3].  When CR1NV[3]=0, the nonvolatile version of the BP bits (SR1NV[4:2]), is used to control Block Protection and the Write Register (WRR) command writes SR1NV[4:2] and updates SR1V[4:2] with the same value. When CR1NV[3]=1, the volatile version of the BP bits (SR1V[4:2]), is used to control Block Protection and the WRR command writes SR1V[4:2] and does not affect SR1NV[4:2].  The CR1NV[3] bit (BPNV_O) should remain in the default state, set as “0” = nonvolatile.  Keeping CR1NV[3] set as default “0” = nonvolatile, during Power-On Reset (POR), hardware reset, or software reset, the bit values in SR1NV[4:2] will be copied to SR1V[4:2], as the default value for the SR1V[4:2] volatile bits.  If CR1NV[3] is set at “1” = volatile, SR1V[4:2] volatile (BP 2-0) bits will be set to binary 111 after Power-on-Reset (POR), hardware reset, or software reset. See Table 2 and Table 3.

CR1NV[5] (TBPROT_O): When TBPROT_O is set to a “0” (default value when shipped from Infineon), the Block Protection is defined to start from the top (maximum address) of the array. When TBPROT_O is set to a “1”, the Block Protection is defined to start from the bottom (zero address) of the array. The desired state of TBPROT_O must be selected during the initial configuration of the device during system manufacture; before the first program or erase operation on the main flash array. CR1NV[5] (TBPROT_O) must not be programmed after programming or erasing is done in the main flash array.

Table 2. Configuration Register 1 Nonvolatile (CR1NV)

Table 3. Lower Array Start of Protection (TBPROT_O = 1)

Summary

With the combination of the Status Register-1 nonvolatile bits BP2, BP1, BP0 (SR1NV[4:2]) and the Configuration Register-1 nonvolatile Bit 5 CR1NV[5] (TBPROT_O) an address range within the main memory array will be protected from program and erase operations.  However, the desired state of TBPROT_O must be selected during the initial configuration of the device during system manufacture, before the first program or erase operation on the main flash array.  CR1NV[5] (TBPROT_O) must not be programmed after programming or erasing is done in the main flash array.  With regards to the CR1NV[3] bit (BPNV_O), it should remain in the default state, set as “0” (nonvolatile), as during POR, hardware reset, or software reset, the bit values in SR1NV[4:2] will be copied, as the default bit values for SR1V[4:2] volatile bits. 

For more details, see the S25FS512S Datasheet.

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Question:

Is it possible to use a combination of two different sizes of data fields for buffers/FIFO elements of the CAN FD Controller?

Answer:

No, it is not possible to configure Tx buffer element's data field to different sizes. The CANFDx_CHy_TXESC register allows you to configure the data field size of the Tx buffer element to up to 64 bytes. This configuration applies to all Tx buffers for the respective channel. The same restriction is applicable for Rx buffers/FIFO elements also; different Rx buffer elements belonging to the same CAN channel cannot have different sizes of the data field. The data field size of the Rx Buffer/FIFO elements can be configured through the CANFDx_CHy_RXESC register ('x' is the CAN FD instance number and 'y' is the channel number in the respective CAN FD group).

For more details, see the “CAN FD Controller” section of the Technical Reference Manual.

Note: This KBA applies to the following series of Traveo II MCUs:

• CYT2 Series
• CYT3 Series
• CYT4 Series

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Question:

How can I get the CPU board to operate only at 3.3 V?

Answer:

Ensure that the jumper settings are as follows:

• J23: Short between pin2 and pin3 (The 3.3 V power rail on the board is enabled).
• J9: Open between pin1 and pin2 (Power-on-reset for +5 V is disabled).

For more information, see the documentation available with the CYTVII-B-E-1M-176-CPU evaluation board.

Note: This KBA applies to the following series of Traveo II MCUs:

• Traveo II for Body CYT2B7 Series

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Question:

What kind of type of XTAL used for external crystal oscillator (ECO)?

Answer:

Crystal Unit and Ceramic Resonator can be used for ECO. Traveo II has a built-in ECO gain control amplifier and can support various Xtals by setting the amplifier parameters.

Amplifier parameters are calculated using the specifications of Xtal. For more details, see the “Clocking System” section of the Architecture Technical Reference Manual and the ECO User Guide. If the calculation result of an XTAL is out of the specified range, the corresponding Xtal cannot be used.

Note: This KBA applies to the following series of Traveo II MCUs:

• CYT2 Series
• CYT3 Series
• CYT4 Series

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Question1:
What is the default I/O drive strength of FX3/FX3S and how can it be configured?

Answer:
As mentioned in section 10.4.4 of the FX3 TRM, the default I/O drive strength is Half Strength. The I/O Drive Strength Configuration Register, GCTL_DS, is configured with a default value of 2, which corresponds to Half Strength according to the following table from the FX3 TRM.

Table 1. Drive Strength Values

The drive strength for I/O pins is programmable even if the pin is configured for an alternate function. The I/O pin drive strength can be set to quarter strength, half strength, three-quarter strength, or full strength by configuring the appropriate bits in the GCTL_DS register. In the FX3 SDK, I/Os on the FX3 device are grouped into multiple interfaces (GPIF, I2C, I2S, SPI, UART) based on function. Refer to the FX3 API Guide of the FX3 SDK for details about APIs used for configuring the drive strength of these interfaces.

Note: FX3S’s S-port I/O drive strength is programmable similar to any other I/O pin as discussed in 4.1.2 I/O Drive Strength of the FX3 TRM.

Question2:
What are the I_OH and I_OL values for different drive strengths?

Answer:
I_OH and I_OL values for different strengths are mentioned in Table 9 of the FX3 datasheet.

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Question:

How do you test USB Host and USB OTG examples of FX3 SDK?

Answer:

The USB Host and USB OTG examples of the FX3 SDK (Path: FX3 SDK Installation Path\Cypress\EZ-USB FX3 SDK\1.3\firmware\basic_examples) can be tested using a custom board.

These examples cannot be tested on the SuperSpeed Explorer kit (CYUSB3KIT-003) due to the following reasons:

• The OTG_ID pin of EZ-USB FX3 is left unconnected in the SuperSpeed Explorer kit, which allows FX3 to be used as a USB device only. This pin must be connected to ground if FX3 is used as a dual-role device.
• EZ-USB FX3 does not contain a charge pump; therefore, it cannot source the VBUS supply when used as an OTG-A device or USB Host. When FX3 is used in an OTG-A mode or as USB Host, an external charge pump, either standalone or integrated in a PMIC, must be used to power VBUS. The USB Host and USB OTG examples control VBUS supply using GPIO 21. The SuperSpeed Explorer kit does not have an external power supply/charge pump that can be controlled using a GPIO to drive the VBUS.
• When using the USB port, one of the VBATT/VBUS supplies is required to power the USB I/O. In the examples, when FX3 is used as a USB Host/OTG-A device, the USB block is configured to work off VBATT power instead of VBUS. However, the VBATT pin of FX3 is left unconnected in the SuperSpeed Explorer kit and hence cannot be used.

The USB Host and USB OTG examples of the FX3 SDK cannot be tested on the FX3 DVK (CYUSB3KIT-001) as done in application note AN77960 because the FX3 DVK is obsolete.

It is recommended to develop a custom FX3 board similar to FX3 DVK and follow AN77960 to test the USB Host and USB OTG examples on FX3. Refer to the FX3 DVK board schematics and AN70707: EZ-USB FX3/FX3S Hardware Design Guidelines and Schematic Checklist for the custom board design.

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Question:

What kind of type of XTAL used for external crystal oscillator (ECO)?

Answer:

Crystal Unit and Ceramic Resonator can be used for ECO. Traveo II has a built-in ECO gain control amplifier and can support various Xtals by setting the amplifier parameters.

Amplifier parameters are calculated using the specifications of Xtal. For more details, see the “Clocking System” section of the Architecture Technical Reference Manual and the ECO User Guide. If the calculation result of an XTAL is out of the specified range, the corresponding Xtal cannot be used.

Note: This KBA applies to the following series of Traveo II MCUs:

• CYT2 Series
• CYT3 Series
• CYT4 Series