Wrong Register Access SCIS01 and SCIS23 in adc.c in PDL 2.1.0 - KBA229088
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Author: TakashiM_61 Version: **
Translation - Japanese: PDL 2.1.0のadc.cにある間違えたレジスタアクセスSCIS01およびSCIS23 – KBA229088 - Community Translated (JA)
Question: Why are the SCIS01 and SCIS23 registers accessed with 8 bits in adc.c, even though these registers have a width of 16 bits?
Answer:
In the ADC device driver contained in PDL 2.1.0, the access to the Scan Conversion Input Selection Registers SCIS01 and SCIS23 are implemented in the adc.c file.
// Set Scan Conversion Input Selection Register
pstcAdc->SCIS01 = (uint8_t)(0x0000FFFFul & pstcConfig->pstcScanInit->u32ScanCannelSelect.u32AD_CHn);
pstcAdc->SCIS23 = (uint8_t)((0xFFFF0000ul & pstcConfig->pstcScanInit->u32ScanCannelSelect.u32AD_CHn) >> 16u);
The above code snippet is incorrect.
According to FM0+ Family Peripheral Manual Analog Macro Part , these registers have a width of 16 bits. If the SCIS01 and SCIS registers are accessed with 8 bits cast “(uint8_t)” as mentioned in the above code snippet, the 8 most significant bits (MSbs) are ignored.
This means that Channel 8 to 15 in SCIS01 register and Channel 24 to 31 in SCIS23 register cannot be selected with above implementation.
Therefore, the following is the correct code of adc.c in PDL 2.1.0:
// Set Scan Conversion Input Selection Register
pstcAdc->SCIS01 = (uint16_t)(0x0000FFFFul & pstcConfig->pstcScanInit->u32ScanCannelSelect.u32AD_CHn);
pstcAdc->SCIS23 = (uint16_t)((0xFFFF0000ul & pstcConfig->pstcScanInit->u32ScanCannelSelect.u32AD_CHn) >> 16u);